Department of Electrical and Computer Engineering

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Presentation transcript:

Department of Electrical and Computer Engineering ECE 4371, Fall, 2015 Introduction to Telecommunication Engineering/Telecommunication Laboratory                                                             Zhu Han Department of Electrical and Computer Engineering Class 14 Oct. 13th, 2015

Outline Match Filter Equalizer Timing

Receiver Structure Matched filter: match source impulse and maximize SNR grx to maximize the SNR at the sampling time/output Equalizer: remove ISI Timing When to sample. Eye diagram Decision d(i) is 0 or 1 Figure 7.20 Noise na(t) d(i) gTx(t) gRx(t) ?

Matched Filter Input signal s(t)+n(t) Maximize the sampled SNR=s(T0)/n(T0) at time T0

Matched filter example Received SNR is maximized at time T0 Matched Filter: optimal receive filter for maximized example: transmit filter receive filter (matched)

Matched Filter

Matched Filter

Matched Filter

Matched Filter Since g(t)

Properties of Matched Filters

Equalizer When the channel is not ideal, or when signaling is not Nyquist, There is ISI at the receiver side. In time domain, equalizer removes ISR. In frequency domain, equalizer flat the overall responses. In practice, we equalize the channel response using an equalizer

Zero-Forcing Equalizer The overall response at the detector input must satisfy Nyquist’s criterion for no ISI: The noise variance at the output of the equalizer is: If the channel has spectral nulls, there may be significant noise enhancement.

Transversal Transversal Zero-Forcing Equalizer If Ts<T, we have a fractionally-spaced equalizer For no ISI, let:

Zero-Forcing Equalizer continue Zero-forcing equalizer, figure 7.22 and example 7.3 Example: Consider a baud-rate sampled equalizer for a system for which Design a zero-forcing equalizer having 5 taps.

MMSE Equalizer In the ISI channel model, we need to estimate data input sequence xk from the output sequence yk Minimize the mean square error.

Adaptive Equalizer Adapt to channel changes; training sequence

Decision Feedback Equalizer To use data decisions made on the basis of precursors to take care of postcursors Consists of feedforward, feedback, and decision sections (nonlinear) DFE outperforms the linear equalizer when the channel has severe amplitude distortion or shape out off.

Different types of equalizers Zero-forcing equalizers ignore the additive noise and may significantly amplify noise for channels with spectral nulls Minimum-mean-square error (MMSE) equalizers minimize the mean-square error between the output of the equalizer and the transmitted symbol. They require knowledge of some auto and cross-correlation functions, which in practice can be estimated by transmitting a known signal over the channel Adaptive equalizers are needed for channels that are time-varying Blind equalizers are needed when no preamble/training sequence is allowed, nonlinear Decision-feedback equalizers (DFE’s) use tentative symbol decisions to eliminate ISI, nonlinear Ultimately, the optimum equalizer is a maximum-likelihood sequence estimator, nonlinear

Timing Extraction Received digital signal needs to be sampled at precise instants. Otherwise, the SNR reduced. The reason, eye diagram Three general methods Derivation from a primary or a secondary standard. GPS, atomic closk Tower of base station Backbone of Internet Transmitting a separate synchronizing signal, (pilot clock, beacon) Satellite Self-synchronization, where the timing information is extracted from the received signal itself Wireless Cable, Fiber

Example Self Clocking, RZ Contain some clocking information. PLL

Timing/Synchronization Block Diagram After equalizer, rectifier and clipper Timing extractor to get the edge and then amplifier Train the phase shifter which is usually PLL Limiter gets the square wave of the signal Pulse generator gets the impulse responses

Timing Jitter Random forms of jitter: noise, interferences, and mistuning of the clock circuits. Pattern-dependent jitter results from clock mistuning and, amplitude-to-phase conversion in the clock circuit, and ISI, which alters the position of the peaks of the input signal according to the pattern. Pattern-dependent jitter propagates Jitter reduction Anti-jitter circuits Jitter buffers Dejitterizer