Yen-Ting Yu Iris Hui-Ru Jiang Yumin Zhang Charles Chiang DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification ICCAD’14.

Slides:



Advertisements
Similar presentations
Linear Time Algorithm to Find All Relocation Positions for EUV Defect Mitigation Yuelin Du, Hongbo Zhang, Qiang Ma and Martin D. F. Wong ASPDAC13.
Advertisements

Wall Building for RTS Games Patrick Schmid. Age of Empires.
Indexing DNA Sequences Using q-Grams
 Over-all: Very good idea to use more than one source. Good motivation (use of graphics). Good use of simplified, loosely defined -- but intuitive --
Mining Compressed Frequent- Pattern Sets Dong Xin, Jiawei Han, Xifeng Yan, Hong Cheng Department of Computer Science University of Illinois at Urbana-Champaign.
Efficient High-Resolution Stereo Matching using Local Plane Sweeps Sudipta N. Sinha, Daniel Scharstein, Richard CVPR 2014 Yongho Shin.
Efficient Process-Hotspot Detection Using Range Pattern Matching in Routing Stage Hailong Yao 1 Subarna Sinha 2 Charles Chiang 2 Xianlong Hong 1 Yici Cai.
Correlation Search in Graph Databases Yiping Ke James Cheng Wilfred Ng Presented By Phani Yarlagadda.
Native-Conflict-Aware Wire Perturbation for Double Patterning Technology Szu-Yu Chen, Yao-Wen Chang ICCAD 2010.
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography Bei Yu, Xiaoqing Xu, JhihRong Gao, David Z. Pan.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Is Your Layout Density Verification Exact ? Hua Xiang *, Kai-Yuan Chao ‡, Ruchir Puri * and D.F. Wong + * IBM T.J. Watson Research Center + Univ. of Illinois.
Texture Segmentation Based on Voting of Blocks, Bayesian Flooding and Region Merging C. Panagiotakis (1), I. Grinias (2) and G. Tziritas (3)
GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology Yue Xu, Chris Chu Iowa State University Form ICCAD2009.
Ahmed Awad Atsushi Takahash Satoshi Tanakay Chikaaki Kodamay ICCAD’14
1 Minimum Ratio Contours For Meshes Andrew Clements Hao Zhang gruvi graphics + usability + visualization.
MCFRoute: A Detailed Router Based on Multi- Commodity Flow Method Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li.
Dual Graph-Based Hot Spot Detection Andrew B. Kahng 1 Chul-Hong Park 2 Xu Xu 1 (1) Blaze DFM, Inc. (2) ECE, University of California at San Diego.
Text Detection in Video Min Cai Background  Video OCR: Text detection, extraction and recognition  Detection Target: Artificial text  Text.
1 Last lecture  Path planning for a moving Visibility graph Cell decomposition Potential field  Geometric preliminaries Implementing geometric primitives.
1. Elements of the Genetic Algorithm  Genome: A finite dynamical system model as a set of d polynomials over  2 (finite field of 2 elements)  Fitness.
Placement of Integration Points in Multi-hop Community Networks Ranveer Chandra (Cornell University) Lili Qiu, Kamal Jain and Mohammad Mahdian (Microsoft.
Fast and Area-Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts Charles Chiang, Synopsys Andrew B. Kahng, UC San Diego Subarna.
SubSea: An Efficient Heuristic Algorithm for Subgraph Isomorphism Vladimir Lipets Ben-Gurion University of the Negev Joint work with Prof. Ehud Gudes.
Design Bright-Field AAPSM Conflict Detection and Correction C. Chiang, Synopsys A. Kahng, UC San Diego S. Sinha, Synopsys X. Xu, UC San Diego A. Zelikovsky,
Iris localization algorithm based on geometrical features of cow eyes Menglu Zhang Institute of Systems Engineering
1 Efficient Placement and Dispatch of Sensors in a Wireless Sensor Network Prof. Yu-Chee Tseng Department of Computer Science National Chiao-Tung University.
A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography Hsi-An Chien, Szu-Yuan Han, Ye-Hong Chen, and Ting-Chi Wang Department of.
Sambuddha Bhattacharya Subramanian Rajagopalan Shabbir H. Batterywala Fixing Double Patterning Violations With Look-Ahead ASD-DAC’14.
Triple Patterning Aware Detailed Placement With Constrained Pattern Assignment Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D.F. Wong.
Constrained Pattern Assignment for Standard Cell Based Triple Patterning Lithography H. Tian, Y. Du, H. Zhang, Z. Xiao, M. D.F. Wong Department of ECE,
Optimally Minimizing Overlay Violation in Self-aligned Double Patterning Decomposition for Row-based Standard Cell Layout in Polynomial Time Z. Xiao, Y.
Exposure In Wireless Ad-Hoc Sensor Networks S. Megerian, F. Koushanfar, G. Qu, G. Veltri, M. Potkonjak ACM SIG MOBILE 2001 (Mobicom) Journal version: S.
Abstract A new Open Artwork System Interchange Standard (OASIS) has been recently proposed for replacing the GDSII format. A primary objective of the new.
1 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and.
Fast Subsequence Matching in Time-Series Databases Christos Faloutsos M. Ranganathan Yannis Manolopoulos Department of Computer Science and ISR University.
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
Accurate Process-Hotspot Detection Using Critical Design Rule Extraction Y. Yu, Y. Chan, S. Sinha, I. H. Jiang and C. Chiang Dept. of EE, NCTU, Hsinchu,
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Hongbo Zhang, Yuelin Du, Martin D.F. Wong, Yunfei Deng, Pawitter Mangat Synopsys Inc., USA Dept. of ECE, Univ. of Illinois at Urbana-Champaign GlobalFoundries.
Global Routing.
1 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese.
1 Global Routing Method for 2-Layer Ball Grid Array Packages Yukiko Kubo*, Atsushi Takahashi** * The University of Kitakyushu ** Tokyo Institute of Technology.
K.Yuan, J.Yang and D.Pan ECE Dept. Univ. of Texas at Austin
Approximation algorithms for TSP with neighborhoods in the plane R 郭秉鈞 R 林傳健.
Tao Lin Chris Chu TPL-Aware Displacement- driven Detailed Placement Refinement with Coloring Constraints ISPD ‘15.
Boolean Minimizer FC-Min: Coverage Finding Process Petr Fišer, Hana Kubátová Czech Technical University Department of Computer Science and Engineering.
Register Placement for High- Performance Circuits M. Chiang, T. Okamoto and T. Yoshimura Waseda University, Japan DATE 2009.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
Configurable Multi-product Floorplanning Qiang Ma, Martin D.F. Wong, Kai-Yuan Chao ASP-DAC 2010.
Self-Aligned Double Patterning Decomposition for Overlay Minimization and Hot Spot Detection H. Zhang, Y. Du, M. D.F. Wong, R. Topaloglu Dept. of ECE,
Cristian Andrades M. Andrea Rodr´ıguez Charles C. Chiang Signature Indexing of Design Layouts for Hotspot Detection DATE’14.
Rectlinear Block Packing Using the O-tree Representation Yingxin Pang Koen Lampaert Mindspeed Technologies Chung-Kuan Cheng University of California, San.
Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald Graham CSE Dept., University of California, San Diego, CA Character Design and Stamp Algorithms.
Hsing-Chih Chang Chien Hung-Chih Ou Tung-Chieh Chen Ta-Yu Kuan Yao-Wen Chang Double Patterning Lithography-Aware Analog Placement.
An Efficient Linear Time Triple Patterning Solver Haitong Tian Hongbo Zhang Zigang Xiao Martin D.F. Wong ASP-DAC’15.
Computer Science and Engineering TreeSpan Efficiently Computing Similarity All-Matching Gaoping Zhu #, Xuemin Lin #, Ke Zhu #, Wenjie Zhang #, Jeffrey.
Chin-Hsiung Hsu, Yao-Wen Chang, and Sani Rechard Nassif From ICCAD09.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
Concepts and Realization of a Diagram Editor Generator Based on Hypergraph Transformation Author: Mark Minas Presenter: Song Gu.
Two Finger Caging of Concave Polygon Peam Pipattanasomporn Advisor: Attawith Sudsang.
Compressing Bi-Level Images by Block Matching on a Tree Architecture Sergio De Agostino Computer Science Department Sapienza University of Rome ITALY.
NanoCAD Lab UCLA Effective Model-Based Mask Fracturing Heuristic Abde Ali Kagalwalla and Puneet Gupta NanoCAD Lab Department of Electrical Engineering,
1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.
Prof. Yu-Chee Tseng Department of Computer Science
Fill Area Algorithms Jan
Donghui Zhang, Tian Xia Northeastern University
Presentation transcript:

Yen-Ting Yu Iris Hui-Ru Jiang Yumin Zhang Charles Chiang DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification ICCAD’14

Outline Introduction Preliminaries Hotspot Detection Framework Experimental Result Conclusion

Introduction In modern manufacturing processes, certain layout configurations are susceptible to lithographic process Patterns with similar layouts could become process- hotspots Represent these similar patterns by a representative pattern with edge tolerances and incomplete specified regions

String-matching-based  Each pattern and layout window are encoded by strings

Overview

The key features of this work  Redefine MTCG and the extraction rules to reflect the impacts of don’t care regions and edge tolerances  DRC searching space reduction technique  Longest common subsequence on strings to handle the impact of don’t care regions

Preliminaries Design Rule Checking (DRC)  Design rules are a set of parameters to ensure the manufacturability of a layout  Fundamental rules include the minimum width, minimum spacing, and minimum enclosure rules

Modified Transitive Closure Graph (MTCG)

Problem Formulation Given  Hotspot pattern with edge tolerances and incompletely specified regions (don’t care regions)  A layout Report  All hotspot locations considering eight possible orientations in the layout

Hotspot Detection Framework

Pattern Enumeration Edge tolerances within a given pattern may lead to different pattern topologies Extend the idea of All-Pair Min-Range Path (APMRP) algorithm to form pattern enumeration algorithm

APMRP  m and n denote the minimum and maximum distance between two edges  minimize the (n – m) value  If m 0 (m, n) set contains three subsets: {(m, −1), (0, 0), (1, n)}  If m < 0 and n = 0 (m, n) set contains two subsets: {(m, −1), (0, 0)}  If m = 0 and n > 0 (m, n) set contains two subsets: {(0, 0), (1, n)}  Else only one subset {(m, n)}

MTCG with Don’t Care Regions and Critical DRC Rule Extraction To use the aid of DRC to realize hotspot detection Interpret all edge constraints to design rules Redefine five types of rules in [1] All rules can be extracted only from C h,h and C v,v, C h,v and C v,h are serve for boundary checking

Rule 1(internal rule)–the width and height of a block tile  find the dimension of each block tile that does not touch the window boundary

Rule 2(external rule)–the distance between two adjacent block tiles  find the dimensions of all space tiles that do not touch the window boundary and are located in between block tiles

Rule 3(diagonal rule)–the diagonal relations between two convex corners of block (space) tiles  find the diagonal relations between any two convex corners of block (space) tiles

Rule 4(longedge rule)–the space or block tile with one edge touching the window boundary

Rule 5(segment rule)–the space tile with two or three adjacent edges touching the window boundary or space tiles

The dimensions of each extracted rule can be represented by a rule rectangle The height and width of a rule rectangle are defined by its corresponding edge constraints

Define two types of don’t care regions  Don’t region with two or three adjacent edges fully facing the window boundaries  Don’t region in between two facing edges of polygons

Rule 6––the space tile with one edge or two opposite edges touching the boundary tiles

Searching Space Reduction A pattern may have eight possible orientations Divide these eight orientations into two sets Generate a runset file for each set and run DRC twice to obtain the locations that hit any generated rule

The region AND technique

Rule Ordering Even a simple range pattern may generate tons of different pattern topologies after pattern enumeration With the region AND technique, how to cover the whole pattern topologies during DRC with fewest DRC rules becomes an issue

The topology covering problem is NP-hard  U = {1, 2, 3, 4, 5} four subsets S = {{1, 2, 3}, {2, 4}, {3, 4}, {4, 5}} subsets{1, 2, 3} {4, 5} A greedy heuristic can be applied to this problem

Rules priority  {internal rule, external rule, diagonal rule} v {longedge rule, sixth rule} v {segment rule}

Candidate Identification Each generated pattern topology is represented by a set of DRC rules Encoding rule rectangles to two strings, one in the vertical, one in the horizontal

To identify the potential hotspot locations in the layout, based on DRC results and rule priorities

Finalization Some locations contain extra polygons that are not related to any of our extracted DRC rules and are not within the don’t care regions

Experimental Result Implemented in the C programming language on a Linux platform Hotspot patterns

Integrate a state-of-the-art industrial DRC engine into our framework

Conclusion Proposed an accurate and efficient hotspot detection framework to handle hotspot patterns with edge tolerances and incompletely specified regions Compared with the state-of-the-art work, our approach can reach promising success rate with significant speedups