Nick McKeown Spring 2012 Lecture 2,3 Output Queueing EE384x Packet Switch Architectures.

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Presentation transcript:

Nick McKeown Spring 2012 Lecture 2,3 Output Queueing EE384x Packet Switch Architectures

Outline 1.Output Queued Switches 2.Rate and Delay guarantees

Output queued switch Link 1 Link 2 Link 3 Link 4 Link 1, ingressLink 1, egress Link 2, ingressLink 2, egress Link 3, ingressLink 3, egress Link 4, ingressLink 4, egress Link rate, R R R R R R R

Characteristics Arriving packets immediately written to output queue. Isolation: Packets unaffected by packets to other outputs. Work conserving: an output line is always busy when there is a packet in the switch for it. Throughput: Maximized. Average delay: Minimized. We can control the rate of individual flows, and the delay of individual packets

The shared memory switch Link 1, ingressLink 1, egress Link 2, ingressLink 2, egress Link 3, ingressLink 3, egress Link N, ingressLink N, egress A single pool of memory R R R R R R

Questions Is a shared memory switch work conserving? How does average packet delay compare to an output queued switch? Packet loss?

Memory bandwidth OQ switch Per output: (N+1)R Switch total: NR(N+1)  N 2 R Shared Memory Switch: Switch total: 2NR

Capacity of shared memory switches Shared Memory 64 byte bus 2ns SRAM 1 2 N Assume: 1. 2ns random access SRAM MHz bus; separate read and write 3. 64byte wide bus 4. Smallest packet size = 64bytes 500MHz * 64bytes * 8  ~= 256Gb/s

Outline 1.Output Queued Switches 2.Rate and Delay guarantees

Rate Guarantees Problem #1: In a FIFO queue, all packets and flows receive the same service rate. Solution: Place each flow in its own output queue; serve each queue at a different rate.

Fairness 1.1 Mb/s 10 Mb/s 100 Mb/s A B R1R1 C 0.55 Mb/s 0.55 Mb/s What is the “fair” allocation: (0.55Mb/s, 0.55Mb/s) or (0.1Mb/s, 1Mb/s)? e.g. an http flow with a given (IP SA, IP DA, TCP SP, TCP DP)

Fairness 1.1 Mb/s 10 Mb/s 100 Mb/s A B R1R1 D What is the “fair” allocation? 0.2 Mb/s C

Max-Min Fairness A common way to allocate flows N flows share a link of rate C. Flow f wishes to send at rate W(f), and is allocated rate R(f). 1.Pick the flow, f, with the smallest requested rate. 2.If W(f) < C/N, then set R(f) = W(f). 3.If W(f) > C/N, then set R(f) = C/N. 4.Set N = N – 1. C = C – R(f). 5.If N>0 goto 1.

1 W(f 1 ) = 0.1 W(f 3 ) = 10 R1R1 C W(f 4 ) = 5 W(f 2 ) = 0.5 Max-Min Fairness An example Round 1: Set R(f 1 ) = 0.1 Round 2: Set R(f 2 ) = 0.9/3 = 0.3 Round 3: Set R(f 4 ) = 0.6/2 = 0.3 Round 4: Set R(f 3 ) = 0.3/1 = 0.3

Max-Min Fairness How can a router “allocate” different rates to different flows? First, let’s see how a router can allocate the “same” rate to different flows…

Fair Queueing 1.Packets belonging to a flow are placed in a FIFO. This is called “per-flow queueing”. 2.FIFOs are scheduled one bit at a time, in a round- robin fashion. 3.This is called Bit-by-Bit Fair Queueing. Flow 1 Flow N ClassificationScheduling Bit-by-bit round robin

Weighted Bit-by-Bit Fair Queueing Likewise, flows can be allocated different rates by servicing a different number of bits for each flow during each round. 1 R(f 1 ) = 0.1 R(f 3 ) = 0.3 R1R1 C R(f 4 ) = 0.3 R(f 2 ) = 0.3 Order of service for the four queues: … f 1, f 2, f 2, f 2, f 3, f 3, f 3, f 4, f 4, f 4, f 1,… Also called “Generalized Processor Sharing (GPS)”

Packetized Weighted Fair Queueing (WFQ) Problem: We need to serve a whole packet at a time. Solution: 1.Determine what time a packet, p, would complete if we served flows bit-by-bit. Call this the packet’s finishing time, F. 2.Serve packets in the order of increasing finishing time. Theorem: Packet p will depart before F + TRANSP max Also called “Packetized Generalized Processor Sharing (PGPS)”

Intuition behind Packetized WFQ 1.Consider packet p that arrives and immediately enters service under WFQ. 2.Potentially, there are packets Q = {q, r, …} that arrive after p that would have completed service before p under bit-by-bit WFQ. These packets are delayed by the duration of p’s service. 3.Because the amount of data in Q that could have departed before p must be less than or equal to the length of p, their ordering is simply changed. 4.Packets in Q are delayed by the maximum duration of p. (Detailed proof in Parekh and Gallager)

Calculating F Assume that at time t there are N(t) active (non-empty) queues. Let R(t) be the number of rounds in a round-robin service discipline of the active queues, in [0,t]. A P bit long packet entering service at t 0 will complete service in round R(t) = R(t 0 ) + P.

An example of calculating F Flow 1 Flow i Flow N Calculate S i and F i & Enqueue Pick packet with smallest F i & Send  In both cases, F i = S i + P i  R(t) is monotonically increasing with t, therefore same departure order in R(t) as in t. Case 1: If packet arrives to non-empty queue, then S i = F i-1 Case 2: If packet arrives at t 0 to empty queue, then S i = R(t 0 ) R(t)R(t)

WFQ is complex 1.There may be hundreds to millions of flows; the linecard needs to manage a FIFO per flow. 2.The finishing time must be calculated for each arriving packet, 3.Packets must be sorted by their departure time. Naively, with m packets, the sorting time is O(logm). 4.In practice, this can be made to be O(logN), for N active flows : N Packets arriving to egress linecard Calculate F p Find Smallest F p Departing packet Egress linecard

Delay Guarantees Problem #2: In a FIFO queue, the delay of a packet is determined by the number of packets ahead of it (from other flows). Solution: Control the departure time of each packet.

Simple deterministic model A(t)A(t) D(t)D(t) Cumulative number of departed bits up until time t. time Service Process, rate R Cumulative number of bits Cumulative number of bits that arrived up until time t. R A(t)A(t) D(t)D(t) Q(t)Q(t) Properties of A(t), D(t): 1. A(t), D(t) are non-decreasing 2. A(t) >= D(t)

D(t) A(t) time Q(t) d(t) Queue occupancy: Q(t) = A(t) - D(t). Queueing delay, d(t), is the time spent in the queue by a bit that arrived at time t, (assuming that the queue is served FCFS/FIFO). Simple Deterministic Model Cumulative number of bits

time Cumulative bytes A(t) D(t)  Q(t) Deterministic analysis of a router queue FIFO delay, d(t) R A(t)D(t) Model of router queue Q(t)

So how can we control the delay of packets? Assume continuous time, bit-by-bit flows for a moment… 1.Let’s say we know the arrival process, A f (t), of flow f to a router. 2.Let’s say we know the rate, R(f) that is allocated to flow f. 3.Then, in the usual way, we can determine the delay of packets in f, and the buffer occupancy.

Flow 1 Flow N Classification WFQ Scheduler A 1 (t) A N (t) R(f 1 ), D 1 (t) R(f N ), D N (t) time Cumulative bytes A 1 (t) D 1 (t) R(f1)R(f1) Key idea: In general, we don’t know the arrival process. So let’s constrain it.

One way to bound the arrival process time Cumulative bytes   Number of bytes that can arrive in any period of length t is bounded by: This is called “(  ) regulation” A 1 (t)

(  ) Constrained Arrivals and Minimum Service Rate time Cumulative bytes A 1 (t) D 1 (t) R(f1)R(f1)   d max B max Theorem [Parekh,Gallager]: If flows are leaky-bucket constrained, and routers use WFQ, then end-to-end delay guarantees are possible.

The leaky bucket “(  )” regulator Tokens at rate,  Token bucket size,  Packet buffer Packets One byte (or packet) per token

How the user/flow can conform to the (  ) regulation Leaky bucket as a “shaper” Tokens at rate,  Token bucket size  Variable bit-rate compression To network time bytes time bytes time bytes  C

Checking up on the user/flow Leaky bucket as a “policer” Tokens at rate,  Token bucket size  time bytes time bytes  C Router From network

Packet switch with QoS Policer Classifier Policer Classifier Per-flow Queue Scheduler Per-flow Queue Scheduler Per-flow Queue Questions: These results assume an OQ switch 1. Why? 2. What happens if it is not?

References 1.Abhay K. Parekh and R. Gallager “A Generalized Processor Sharing Approach to Flow Control in Integrated Services Networks: The Single Node Case” IEEE Transactions on Networking, June M. Shreedhar and G. Varghese “Efficient Fair Queueing using Deficit Round Robin”, ACM Sigcomm, 1995.