A Silicon vertex tracker prototype for CBM Material for the FP6 Design application

Compact tracking with Si-Sensors in CBM Geometry of the SVT section 2 planes at 5 and 10 cm from the target inner diameter 11 mm only 10 9 beam particles per second Single event track densities up to 50 cm -2 SVT in vacuum CBM-STS CBM-SVT  100 cm 2

Tasks of the tracking system Momentum measurement for charged tracks with momentum resolution of O(1%) Material budget Track matching in high track density environment Single track vertex resolution better 30  m High resolution tracking stations close to the target Efficient recognition of electron pairs from  0 decays (Conversion, Dalitz) reconstruction of incomplete tracks highly efficient matching with PID detectors

Technical challenge High track density close to the target and at small angles Mainly affects the pixel sensors Fast readout Event pile-up in case of MAPS Radiation tolerance Possibly high level of slow neutrons Low mass design and mechanics efficient cooling of sensors detectors need to be moved during the runs

Objective of the Design Proposal Design and build a Silicon Vertex Tracker of geometry anticipated for the CBM with MAPS technology achievable in 2 years from now. Study all aspects of such compact high resolution tracking devices with a full size prototype. Aim at a fully operational device with a self triggered readout. Relax conditions on radiation hardness and read-out speed. Work out a detailed design for the complete tracking station of the CBM detector. Optimize design with respect to: vertex resolution track finding efficiency momentum resolution material budget

Substantial R&D already done Taken from Mark Winteri, IReS "DESY PRC proposal"

MAPS for Upgrades & Future Projects Taken from Woijech Dulinski, LEPSI "Frontier Detectors for Frontier Physics"

Project structure Coordination GSI Chip design IRES/LEPSI Strasbourg Qualification GSI Darmstadt DAQ, Construction IKF Darmstadt Design studies MSIP Cracow Space frame KRI/CDBM St. Petersburg

Project planning

Cost Work Package IReS/ LEPSI GSIIKFMSIPEUSum Chip design k€ FTE2-2 Chip qualification k€ FTE112 DAQ k€ FTE1,50,652,15 STS design Studies k€-40 FTE2,80,53,3 Overhead k€30 Sum k€ FTE211,52,82,159,45