Property Directed Reachability (PDR) Using Cubes of Non-state Variables With Property Directed Reachability Using Cubes of Non-state Variables With Property.

Slides:



Advertisements
Similar presentations
The behavior of SAT solvers in model checking applications K. L. McMillan Cadence Berkeley Labs.
Advertisements

Exploiting SAT solvers in unbounded model checking
The Synthesis of Cyclic Circuits with SAT and Interpolation By John Backes and Marc Riedel ECE University of Minnesota.
Solve a System Algebraically
Efficient Implementation of Property Directed Reachability Niklas Een, Alan Mishchenko, Robert Brayton.
Aaron Bradley University of Colorado, Boulder
NP-complete and NP-hard problems Transitivity of polynomial-time many-one reductions Concept of Completeness and hardness for a complexity class Definition.
© Anvesh Komuravelli IC3/PDR Overview of IC3/PDR Anvesh Komuravelli Carnegie Mellon University.
The Analysis of Cyclic Circuits with Boolean Satisfiability John Backes, Brian Fett, and Marc Riedel Electrical Engineering, University of Minnesota.
Reduction of Interpolants for Logic Synthesis John Backes Marc Riedel University of Minnesota Dept.
Algorithms and Data Structures for Logic Synthesis and Verification using Boolean Satisfiability John Backes Advisor: Marc Riedel
SAT and Model Checking. Bounded Model Checking (BMC) A.I. Planning problems: can we reach a desired state in k steps? Verification of safety properties:
1 Boolean Satisfiability in Electronic Design Automation (EDA ) By Kunal P. Ganeshpure.
Bounded Model Checking EECS 290A Sequential Logic Synthesis and Verification.
Pruning techniques for the SAT-based Bounded Model-Checking problem Ofer Shtrichman Weizmann Institute of Science & IBM - HRL.
Using Decision Procedures for Program Verification Christopher Lynch Clarkson University.
Knowledge Representation II (Inference in Propositional Logic) CSE 473 Continued…
Automated Extraction of Inductive Invariants to Aid Model Checking Mike Case DES/CHESS Seminar EECS Department, UC Berkeley April 10, 2007.
Daniel Kroening and Ofer Strichman 1 Decision Procedures in First Order Logic Decision Procedures for Equality Logic.
USING SAT-BASED CRAIG INTERPOLATION TO ENLARGE CLOCK GATING FUNCTIONS Ting-Hao Lin, Chung-Yang (Ric) Huang Graduate Institute of Electrical Engineering,
7/13/2003BMC A SAT-Based Approach to Abstraction Refinement in Model Checking Bing Li, Chao Wang and Fabio Somenzi University of Colorado at Boulder.
SAT-based Model Checking Yakir Vizel Computer Science Department, Technion, Israel Based on slides from K.L. McMillan, A.R. Bradley and Yakir Vizel.
Enhancing and Integrating Model Checking Engines Robert Brayton Alan Mishchenko UC Berkeley June 15, 2009.
It’s All About Properties of Equality. How could properties of equality be applied to solve this equation? Example 1: 3x + 11 = 32 What is the value of.
Incremental formal verification of hardware Hana Chockler Alexander Ivrii Arie Matsliah Shiri Moran Ziv Nevo IBM Research - Haifa.
Cut-Based Inductive Invariant Computation Michael Case 1,2 Alan Mishchenko 1 Robert Brayton 1 Robert Brayton 1 1 UC Berkeley 2 IBM Systems and Technology.
Verification & Validation By: Amir Masoud Gharehbaghi
Finding Models for Blocked 3-SAT Problems in Linear Time by Systematical Refinement of a Sub- Model Gábor Kusper Eszterházy Károly.
SAT-Based Model Checking Without Unrolling Aaron R. Bradley.
PDR: Property Directed Reachability AKA ic3: SAT-Based Model Checking Without Unrolling Aaron Bradley University of Colorado, Boulder University of Colorado,
SAT Solving As implemented in - DPLL solvers: GRASP, Chaff and
Inference in Propositional Logic (and Intro to SAT) CSE 473.
Complexity ©D.Moshkovits 1 2-Satisfiability NOTE: These slides were created by Muli Safra, from OPICS/sat/)
1 Alan Mishchenko Research Update June-September 2008.
Enhancing Model Checking Engines for Multi-Output Problem Solving Alan Mishchenko Robert Brayton Berkeley Verification and Synthesis Research Center Department.
Daniel Kroening and Ofer Strichman 1 Decision Procedures in First Order Logic Decision Procedures for Equality Logic.
On the Relation Between Simulation-based and SAT-based Diagnosis CMPE 58Q Giray Kömürcü Boğaziçi University.
Variable-Time-Frame Gate-Level Abstraction Alan Mishchenko Niklas Een Robert Brayton Alan Mishchenko Niklas Een Robert Brayton UC Berkeley UC Berkeley.
Resolution Proofs as a Data Structure for Logic Synthesis John Backes Marc Riedel Electrical.
Decision Procedures in First Order Logic
Efficient Generation of Small Interpolants in CNF (for Model Checking)
Introduction to Formal Verification
Inference in Propositional Logic (and Intro to SAT)
Hybrid BDD and All-SAT Method for Model Checking
Solving Equations with the Variable on each side
Synthesis for Verification
(xy)(yz)(xz)(zy)
Alan Mishchenko UC Berkeley
Solving Linear Arithmetic with SAT-based MC
Enhancing PDR/IC3 with Localization Abstraction
Synthesis for Verification
Solving Equations by Factoring and Problem Solving
Where Can We Draw The Line?
Property Directed Reachability with Word-Level Abstraction
Introduction to Formal Verification
SAT-Based Area Recovery in Technology Mapping
Solving Systems of Equations using Substitution
Canonical Computation without Canonical Data Structure
Canonical Computation Without Canonical Data Structure
Scalable and Scalably-Verifiable Sequential Synthesis
Automated Extraction of Inductive Invariants to Aid Model Checking
Improvements to Combinational Equivalence Checking
A Progressive Approach for Satisfiability Modulo Theories
Resolution Proofs for Combinational Equivalence
Alan Mishchenko UC Berkeley
Scalability in Model Checking
Alan Mishchenko UC Berkeley
Canonical Computation without Canonical Data Structure
SAT-based Methods: Logic Synthesis and Technology Mapping
Faster Extraction of High-Level Minimal Unsatisfiable Cores
Presentation transcript:

Property Directed Reachability (PDR) Using Cubes of Non-state Variables With Property Directed Reachability Using Cubes of Non-state Variables With Property Directed Reachability PDR is a symbolic model checking algorithm for verifying safety properties. Ternary Valued Simulation With Gate Variables Shifting Time Frames A new SAT-Based algorithm for symbolic model checking has been gaining popularity. This algorithm, referred to as “Incremental Construction of Inductive Clauses for Indubitable Correctness” (IC3) or “Property Directed Reachability” (PDR), uses information learned from SAT instances of isolated time frames to either prove that an invariant exists, or provide a counter example. The information learned between each time frame is recorded in the form of cubes of the state variables. In this work, we study the effect of extending PDR to use cubes of intermediate variables representing the logic gates in the transition relation. We demonstrate that we can improve the runtime for satisfiable benchmarks by up to 3.2X, with an average speedup of 1.23X. Our approach also provides a speedup of up to 3.84X for unsatisfiable benchmarks. Ph.D. Candidate, University of Minnesota Associate Professor, University of Minnesota John Backes Marc Riedel Abstract SAT Results The algorithm solves SAT instances representing discrete time frames in isolation. Variables, Notation and Terms:Trace Properties BenchmarkTime States (s)Frames StatesInv. StatesTime Gates (s)Frames GatesInv. GatesTime Ratio 6s s s bj08amba2g3f bjrb07amba10andenv bjrb07amba3andenv bjrb07amba4andenv bjrb07amba5andenv bjrb07amba6andenv bjrb07amba7andenv bjrb07amba9andenv bob bobcohdoptdcd bobsmi2c cmudme cmudme eijkbs eijks eijks eijks eijks intel intel intel intel intel intel intel intel intel nusmvguidancep nusmvguidancep nusmvguidancep nusmvguidancep nusmvreactorp nusmvreactorp pdtpmscoherence pdtpmsheap pdtpmsretherrtf pdtpmsvsar pdtswvibs8x8p pdtswvqis10x6p pdtswvqis8x8p pdtswvroz10x6p pdtswvroz10x6p pdtswvroz8x8p pdtswvroz8x8p pdtswvsam6x8p pdtswvtma6x4p pdtswvtma6x4p pdtswvtma6x6p pdtswvtma6x6p pdtswvtms10x8p pdtswvtms12x8p pdtswvtms14x8p pdtvisbakery pdtvisbakery pdtvisbakery pdtvisgoodbakery pdtvisgoodbakery pdtvisgoodbakery pdtvisns3p pdtvisns3p pdtvisns3p pdtvisns3p pdtvisns3p pdtvisns3p pdtvisns3p pdtvisns3p pdtvistimeout pdtvisrethersqo pdtvisvending Geometric Average BenchmarkTime States(s)Frames StatesTime Gates (s)Frames GatesTime Ratio abp4p2ff abp4ptimoneg bc57sensorsp bc57sensorsp0neg bc57sensorsp bc57sensorsp1neg bc57sensorsp bc57sensorsp2neg bc57sensorsp intel intel intel intel irstdme irstdme irstdme nusmvtcasp5n nusmvtcastp prodcellp0neg prodcellp prodcellp1neg prodcellp prodcellp2neg prodcellp prodcellp prodcellp4neg Geometric Average Generally better results for satisfiable benchmarks Some unsatisfiable benchmarks proved faster Blocking Phase: Propagation Phase: Why Use Cubes of Gate Variables? x 0,x 1,x 2,x 3 g 0,g 1 x4x Three cubes in terms of x 0,x 1,x 2,x 3 can by blocked by one cube in terms of g 0,g 1 ! UNSAT Results Experiment Original Transition RelationNew Transition Relation Gates g 0,g 1,g 2,g 3 have only state variables in their cone of influence (COI)