PIC – ch. 2b. Move to GPR Move [copy] contents of WREG  GPR/RAM MOVLW99H;WREG=99H MOVWF0H ;move [copy] WREG contents to location 0h … -Cant move literal.

Slides:



Advertisements
Similar presentations
Microprocessors.
Advertisements

Parul Polytechnic Institute Subject Code : Name Of Subject : Microprocessor and assembly language programming Name of Unit : Introduction to Microprossor.
MOV Instruction MOV destination, source ; copy source to dest. MOV A,#55H ;load value 55H into reg. A MOV R0,A ;copy contents of A into R0 ;(now A=R0=55H)
ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
Parul Polytechnic Institute Subject Code : Name Of Subject : Microprocessor and assembly language programming Name of Unit : Introduction to Microprossor.
DAT2343 Comparison of The LMC and General Computer Models © Alan T. Pinck / Algonquin College; 2003.
By Muhammad Ali Mazidi, Rolin McKinlay, Danny Causey
TK 2633 Microprocessor & Interfacing
Room: E-3-31 Phone: Dr Masri Ayob TK 2633 Microprocessor & Interfacing Lecture 1: Introduction to 8085 Assembly Language.
Ch. 5 from Yu & Marut. Registers 14(16-bit) registers: 1.Data reg. – to hold data for an op. 2.Address reg – to hold addr of an instruction or data.
9/20/6Lecture 21 -PIC Architecture1 PIC Architecture Instruction Set.
Micro controllers A self-contained system in which a processor, support, memory, and input/output (I/O) are all contained in a single package.
PIC18 Peripherals.
The 8051 Microcontroller and Embedded Systems
Khaled A. Al-Utaibi  Introduction  Arithmetic Instructions  Basic Logical Instructions  Shift Instructions  Rotate Instructions.
Embedded System Spring, 2011 Lecture 4: The PIC Microcontrollers Eng. Wazen M. Shbair.
Faculty of Engineering, Electrical Department,
Embedded System Spring, 2011 Lecture 10: Arithmetic, Logic Instruction and Programs Eng. Wazen M. Shbair.
ICS312 Set 9 Logic & Shift Instructions. Logic & Shift Instructions Logic and Shift Instructions can be used to change the bit values in an operand. The.
PIC18F Programming Model and Instruction Set
Lecture – 4 PIC18 Family Instruction Set 1. Outline Literal instructions. Bit-oriented instructions. Byte-oriented instructions. Program control instructions.
Embedded System Spring, 2011 Lecture 5: The PIC Microcontrollers Eng. Wazen M. Shbair.
Copyright 2000ELEC 242 Arithmetic Instructions1 Arithmetic Instructions Arithmetic and logical instructions modify the contents of the Flag (Status) register.
Arithmetic Flags and Instructions
Logic Conditional Processing. Status flags - review The Zero flag is set when the result of an operation equals zero. The Carry flag is set when an instruction.
ECE 448 – FPGA and ASIC Design with VHDL George Mason University Lab 1 Introduction to Aldec Active HDL Implementing Combinational Logic in VHDL.
Eng. Husam Alzaq The Islamic Uni. Of Gaza
CHAPTER 6 ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS.
V 0.41 C Arithmetic operators OperatorDescription +, -addition (i+j), subtraction (i-j) *, /multiplication (i*j), division (i/j) ++, --increment (i++),
ECE 447: Lecture 11 Introduction to Programming in Assembly Language.
Department of Electronic & Electrical Engineering Lecture 2. PIC16F84A Architecture / Instructions Memory. Program/Data (Harvard) File Registers (Data).
Chapter 7 Bit Manipulation. 7.1 Logical Operations.
Embedded System Spring, 2011 Lecture 11: Bank Switching Eng. Wazen M. Shbair.
Microprocessor & Assembly Language Arithmetic and logical Instructions.
Microprocessor & Assembly Language
Unit 1 Instruction set M.Brindha AP/EIE
Lecture – 5 Assembly Language Programming
Classification of Instruction Set of 8051
Microprocessor T. Y. B. Sc..
3.Instruction Set of 8085 Consists of 74 operation codes, e.g. MOV
Microprocessor Systems Design I
ICS312 SET 7 Flags.
Introduction to 8085 Instructions
PIC – ch. 2b Md. Atiqur Rahman Ahad.
The FLAGS Register An x bit means an unidentified value 9/12/2018
Assembly Language for Intel-Based Computers, 5th Edition
More on logical instruction and
PIC18 CH. 4.
Data Processing Instructions
Arithmetic and Logic Chapter 5
Memory Organisation Source: under
Arithmetic operations Programming
The 8051 Assembly Language Arithmetic & Logic Instructions
Data Transfers, Addressing, and Arithmetic
Chapter 11 © 2011, The McGraw-Hill Companies, Inc.
And conditional branching
University of Gujrat Department of Computer Science
Chapter 4 Instruction Set.
EECE.3170 Microprocessor Systems Design I
Figure 2-1. PIC WREG and ALU Using Literal Value
EECE.3170 Microprocessor Systems Design I
Basic Building Blocks Multiplexer Demultiplexer Adder +
Arithmetic and Logic Chapter 5
Branching instructions
Basic Building Blocks Multiplexer Demultiplexer Adder +
Chapter 5 Arithmetic and Logic Instructions
ARITHMETIC, LOGIC INSTRUCTIONS, AND PROGRAMS
EECE.3170 Microprocessor Systems Design I
Md. Atiqur Rahman Ahad PIC18… Ch. 3.1 Md. Atiqur Rahman Ahad
Ch. 5 – Intel 8086 – study details from Yu & Marut
Presentation transcript:

PIC – ch. 2b

Move to GPR Move [copy] contents of WREG  GPR/RAM MOVLW99H;WREG=99H MOVWF0H ;move [copy] WREG contents to location 0h … -Cant move literal [immediate] values directly into the general-purpose RAM locations in the PIC18. -They must be moved there via WREG. Q: Can literal values directly into SFR?

ADDWF ADDLW15H; =15h + [WREG] ADDWFfileReg, D; =[WREG] + [fileReg] Sources: Content of WREG fileReg: Content of file register (special or general) Destination: D  indicates destination bit If D = 0, destination of the result is WREG, or If D = 1, destination is file register

Or, ADDWFfileReg, w; =[WREG] + [fileReg] ; destination of the result is WREG ADDWFfileReg, f; =[WREG] + [fileReg] ; destination of the result is fileReg

Q. How to clear WREG?  MOVLW0

Q. State the contents of file reg. RAM locations 12H and WREG after… MOVLW0 ;WREG = 0 MOVWF12H ; move WREG to location 12 to clear it MOVLW22h ; WREG=22 ADDWF12h, F ;add WREG to loc 12h Loc 12h  WREG 

Q. State the contents of file reg. RAM locations 12H and WREG after… MOVLW0 ;WREG = 0 MOVWF12H ; move WREG to location 12 to clear it MOVLW22h ; WREG=22 ADDWF12h, w ;add WREG to loc 12h Loc 12h  WREG 

Table 2.2 ALU instructions – using both WREG & fileReg ADDWFfileReg, d ; d =W / d =F default is F ADDWFCfileReg, d ;… with carry ANDWF- AND IORWF- OR XORWF- Ex-OR w with f SUBFWB- subtract f from w with borrow SUBWF- subtract w from f SUBWFB- subtract w from f with borrow

Table 2.3 File Reg. instructions – using fileReg or WREG as destination COMF fileReg, d ; -complement/invert f DECF-dec f DECFSZ-dec f & skip if zero DECFSNZ -dec f & skip if not zero INC-inc f

MOVF-move fileReg NEGF-negative f Rotate right, rotate left SWAPF-swap nipples in fileReg BTG-bit toggle fileReg

2.4 PIC Status Flag Register The STATUS register is of most importance to programming the PIC, it contains the arithmetic status of the ALU (Arithmetic Logic Unit), the RESET status and the bank select bit for data memory. 8-bit register Only 5 bits to use by PIC18 Other 3 bits – not used and read as 0

C – carry DC – digital carry Z – zero OV– overflow N – negative

C It is affected after an 8-bit addition or subtraction, for unsigned arithmetic Ch. 5

DC – digital carry / Auxiliary carry flag For BCD [binary coded decimal] arithmetic. When there is a carry from bit-3 to bit-4 during an ADD or SUB – it is set, else, cleared.

Z If the result is zero, then Z= 1 Used in arithmetic or logic ops. Z for looping Ch. 3

OV – overflow flag OV = 1, when the result of a signed number operation is too large, causing the high-order bit to overflow into the sign bit. For signed arithmetic  OV, N For unsigned arithmetic  C

N – negative flag For signed no., bit-7 as the sign bit. If bit-7 = 0  Z=0  result is positive If bit-7 = 1  Z=1  result is negative Ch. 5

Some instructions affect all flags – E.g., ADDWL Some inst. – only Z or N flag bits, or both – E.g., ANDWL Some inst. – no flags at all! – E.g., all move instructions, except MOVF

Q. Status of C, DC, Z after addition of 38h and 2Fh for - MOVLW38H ADDLW2FH ========= 38h  Fh  h  WREG = 67h

C = 0 no carry beyond bit#7 DC = 1carry from b#3 to b#4 Z = 0WREG has a value not zero

Q? MOVLW9Ch ADDLW64h

C = 1 DC = 1 Z= 1

See Table 2.4

Conditional branch [jump] InstructionsAction – BCbranch if C = 1 – BNCbranch if C != 0 – BZbranch if Z = 1 – BNZbranch if Z != 0 – BNbranch if N = 1 – BNCbranch if N != 0 – BOVbranch if OV = 1 – BNOV More – ch.3

Next…