Data and Computer Communications Chapter 6 – Digital Data Communications Techniques

Asynchronous and Synchronous Transmission  timing problems require a mechanism to synchronize the transmitter and receiver receiver samples stream at bit intervals receiver samples stream at bit intervals if clocks not aligned, drifting will sample at wrong time after sufficient bits are sent if clocks not aligned, drifting will sample at wrong time after sufficient bits are sent  two techniques to synchronize asynchronous transmission asynchronous transmission synchronous transmission synchronous transmission

Asynchronous Transmission

Asynchronous - Behavior  simple  cheap  overhead of 2 or 3 bits per char (~20%)  good for data with large gaps (keyboard)

Synchronous Transmission  block of data transmitted, sent as a frame  clocks must be synchronized can use separate clock line can use separate clock line or embed clock signal in data or embed clock signal in data  need to indicate start and end of block use preamble and post-amble use preamble and post-amble  more efficient (lower overhead) than asynchronous

Types of Error  an error occurs when a bit is altered between transmission and reception  single bit errors only one bit altered only one bit altered caused by white noise caused by white noise  burst errors contiguous sequence of B bits in which first, last and any number of intermediate bits are in error contiguous sequence of B bits in which first, last and any number of intermediate bits are in error caused by impulse noise or by fading in wireless caused by impulse noise or by fading in wireless effect is greater at higher data rates effect is greater at higher data rates

Error Detection  will have errors  detect using error-detecting code  added by transmitter  recalculated and checked by receiver  still chance of undetected error  parity parity bit set so frame has even number of ones (even parity) or odd number of ones (odd parity) parity bit set so frame has even number of ones (even parity) or odd number of ones (odd parity) even number of bit errors goes undetected even number of bit errors goes undetected

Error Detection Process

Error Detection  P b = Probability a bit is received in error, Bit Error Rate (BER)  P 1 = Probability a frame is received with no error  P 2 = Probability a frame is received with undetected error  F = number of bits / frame  Then, P 1 = (1- P b ) F, P 2 = (1- P 1 )

Error Detection # ISDN has 64 Kbps channel, 1 frame with undetected error per day is expected, (1 frame = 1000 bits), Calculate the number of Frames / day and P 2.  If actual P b = 10 -6, can we achieve the above P 2 ?

Cyclic Redundancy Check  one of most common and powerful checks  for block of k bits, transmitter generates an n-k bit frame check sequence (FCS)  Transmits n bits which is exactly divisible by some number  receiver divides frame by that number if no remainder, assume no error if no remainder, assume no error for math, see Stallings chapter 6 for math, see Stallings chapter 6

Cyclic Redundancy Check  Basis: Modulo-2 arithmetic (X-or for + or -)  Message, M =  Pattern, P = (MSB & LSB = ‘1’)  FCS = ? (5 bits) (01110)  Multiply the Message by 2 5, then divide by the Pattern. Remainder is added with the Message and transmitted.  P is one bit longer than FCS.

Cyclic Redundancy Check Selection of polynomial P: - Should not be divisible by X - Should be divisible by X+1 Benefits: - Detects all burst errors that affect odd number of bits - Detects all burst errors of length less than or equal to degree of the polynomial

Cyclic Redundancy Check - Detects, with high probability, all burst errors of length greater than the degree of the polynomial

Cyclic Redundancy Check # CRC-12 (X 12 + X 11 +X 3 +X+1) Degree: 12 Detects all burst errors that affects odd number of bits, Detects all burst errors of length less than or equal to 12, Detects (99.97 percent of) all burst errors of length more than or equal to 12.

Cyclic Redundancy Check  Digital Logic Implementation:  Message, M = = X 9 + X 7 +X 3 +X 2 +1, Pattern, P = = Poly.?  Register length = FCS  Presence of a gate corresponds to a term in polynomial P, excluding 1 (X 0 ) and X n-k

Error Correction  correction of detected errors usually requires correct data block to be retransmitted  not appropriate for wireless applications bit error rate is high causing lots of retransmissions bit error rate is high causing lots of retransmissions when propagation delay long (satellite) compared with frame transmission time, resulting in retransmission of frame in error plus many subsequent frames when propagation delay long (satellite) compared with frame transmission time, resulting in retransmission of frame in error plus many subsequent frames  instead need to correct errors on basis of bits received  error correction provides this

Error Correction Process

Error Correction  2-dimensional Parity:  “Data is arranged in 2-dimensional array and parity bit is added for each row and column”  P V  “Detects and Corrects all single bit errors”  “Detects all odd number of bit errors and some even P H number of bit errors”

How Error Correction Works  adds redundancy to transmitted message  can deduce original despite some errors  e.g. block error correction code map k bit input onto an n bit codeword map k bit input onto an n bit codeword each distinctly different each distinctly different if get error, assume codeword sent was closest to that received if get error, assume codeword sent was closest to that received  for math, see Stallings chapter 6  Much reduced effective data rate

Block Code Principles  Hamming distance = difference in # of bits,  p = , q = , d (p,q) = ?  Data Code      # Find the distance between all the valid codes (in pairs) on this slide.

Block Code Principles  Received 00100, valid? Can it be corrected?  Find distances and the minimum.  ‘Select the valid code at the minimum distance’  Received 00100, correct word?  More than one minimum distance!!!  (Invalid) => valid and  ‘Equidistance of 2’ => can detect, not correct

Hamming ECC  ‘use of extra parity bits to allow the position identification of a single error’  1. Mark all bit positions that are powers of 2 as parity bits. (positions 1, 2, 4, 8, 16, etc.)  2. All other bit positions are for the data to be encoded. (positions 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, etc.)

Hamming ECC  3. Each parity bit calculates the parity for some of the bits in the code word. The position of the parity bit determines the sequence of bits that it checks.  Position 1: checks bits (1,3,5,7,9,11,...) – Alternate Position 2: checks bits (2,3,6,7,10,11,14,15,...) – Alternate 2-bits  Position 4: checks bits (4,5,6,7,12,13,14,15,20,21,22,23,...) - Alternate 4-bits

Hamming ECC  Position 8: checks bits (8-15,24-31,40- 47,...) – Alternate 8-bits 4. Set the parity bit to create even parity.  A byte of data:  Place the data word, leaving spaces for the parity bits: _ _ 1 _ _ Calculate the parity bits.

Hamming ECC  Position 1 checks bits 1,3,5,7,9,11: ? _ 1 _ _ set position 1 to a 0: 0 _ 1 _ _  Position 2 checks bits 2,3,6,7,10,11: 0 ? 1 _ _ set position 2 to a 1: _ _  Position 4 checks bits 4,5,6,7,12: ? _ set position 4 to a 1: _

Hamming ECC  Position 8 checks bits 8,9,10,11,12: ? set position 8 to a 0:  Final code word:  Finding and fixing a corrupted bit:  Suppose that the word was received as instead.  The method is to verify each check bit.

Hamming ECC  Parity bits 2 and 8 are incorrect. It is = 10, that bit position 10 is the location of the bad bit and needs to be inverted.  # Test if these Hamming-code words are correct. If one is incorrect, indicate the correct code word. Also, indicate what the original data was.   

Problem # For each data unit of following sizes, find the minimum number of redundancy bits needed to correct single bit error (using Hamming code). Specify their positions. a) 12 b) 16 c) 24 d) 64 Find also the utilization of the code space.

Burst Error Correction  Hamming Code can be used:  - Arrange N data elements (with ECC) in two dimension  - Transmit all the first bits from N elements  - Transmit all the second bits from N elements  - And so on …  Organize them as N elements at receiver.

Burst Error Correction  Any burst error of length <= N is seen as a single bit error in a data element and can be corrected.  X2 X1 X0X2 Y2 Z2 X2 X1 X0  Y2 Y1 Y0X1 Y1 Z1 Y2 Y1 Y0  Z2 Z1 Z0X0 Y0 Z0 Z2 Z1 Z0  OriginalTransmitReceived and Organized

Line Configuration - Topology  physical arrangement of stations on medium point to point - two stations point to point - two stations such as between two routers / computerssuch as between two routers / computers multi point - multiple stations multi point - multiple stations traditionally mainframe computer and terminalstraditionally mainframe computer and terminals now typically a local area network (LAN)now typically a local area network (LAN)

Line Configuration - Topology

Line Configuration - Duplex  classify data exchange as half or full duplex  half duplex (two-way alternate) only one station may transmit at a time only one station may transmit at a time requires one data path requires one data path  full duplex (two-way simultaneous) simultaneous transmission and reception between two stations simultaneous transmission and reception between two stations requires two data paths requires two data paths separate media or frequencies used for each directionseparate media or frequencies used for each direction

Summary  asynchronous verses synchronous transmission  error detection and correction  line configurations