Design and Verification of a Layer-2 MAC Classification Engine for a Gigabit Ethernet Switch Jorge Tonfat Ricardo Reis Universidade Federal do Rio Grande do Sul (UFRGS) Instituto de Informática - PPGC/PGMicro

2 MotivationObjectives NetFPGA Platform L2 Classification Engine Verification Methodology Implementation Results ConclusionsOutline

3 Ethernet is the most popular layer 2 protocol. Widely used in LANs and MANs. Ethernet best characteristics: It has a low implementation cost compared with other technologies. High performanceMotivation LAN = Local Area Network MAN = Metropolitan Area Network

4 Design of a L2 classification engine for a Gigabit Ethernet switch deployed at an industrial product. The main function of the Layer-2 classification engine is to forward Ethernet frames to their corresponding output ports. The classification engine should be able to process VLAN frames. (compliant with IEEE 802.1Q)Objectives

5 NetFPGA Platform Developed at Stanford University. Enable fast prototyping of networking hardware. Offers basic hardware modular structure.

6 NetFPGA Platform Frames inside the data pipeline have their own header format. Contains information such as frame size, source port and destination port. New modules can add more headers. NetFPGA module headers Ethernet Frame

7 The L2 switching task needs: MAC address Source Port VLAN ID Related solutions: Binary and Ternary CAMs. Not feasible for large L2 tables. Power hungry and high cost per bit. Software-only switching task. Low performance results. L2 Classification Engine

8 One popular solution: Hashing functions Some disadvantages: Hash collisions. Decreased table capacity. Preferred characteristic: relatively uniform distribution of output values (mem addr) This will reduce the hash collisions and improve the table capacity. L2 Classification Engine To deal with hash collisions, the lookup table is organized in buckets that contain multiple entries.

9 Implements the main function of the Gigabit Ethernet Switch: the frame forwarding and learning. This module is part of the datapath. The classification engine is part of the output port lookup module. L2 Classification Engine

Main Tasks: Frame forwarding. Source MAC address learning. Secondary task: MAC address lookup table aging. Since the SRAM is accessed by three different sources (the forwarding/learning module, the aging module and the external access through the register bus) an arbiter is needed.

11 L2 Classification Engine SRAM arbiter FSM cycles, showing only the memory requests. To achieve the bandwidth of 42 Gbps, each frame is needed to be processed in 8 cycles for a 500 MHz clock. Since 11 cycles are needed to process one frame, two frames are processed interleaved. Remembering that for each cycle, only one kind of request (read/write) is possible. Cycle 7 and Cycle 15 are used to process requests from the aging module and for external access.

12  Design a L2 classification engine... Verification Methodology A testbench environment was developed using SystemVerilog and Modelsim. It is organized in layers. DUV: Design Under Verification

The module was synthesized with different MAC Address lookup table sizes: 4K, 32K, 64K and 128K. All of them obtain an operation frequency of 500 MHz and constant bandwidth of 42 Gbps. It was used Cadence tools and a TSMC standard cell library. Implementation Results SolutionOp. Freq. (MHz) Bandwidth (Gbps) Technology Process This work50042TSMC 180nm [Lau03] nm [Mishra03]10180nm [Papaefstathiou06] UMC 130nm [Papaefstathiou06] has a better bandwidth but is important to note that the bandwidth they show is an average one that depends on the number of collisions and on the size of the table. The results shown are for a 64K table. The ones obtained with a 32K table gives a bandwidth reduced by 25%. The bandwidth in our solution is independent of the table size.

14 The architecture presented in this work achieves the necessary throughput for a 42-port Gigabit Ethernet. It is more time-efficient compared with simpler methods such as direct-test. The results are good ones comparing to other solutions. The functional verification stage allows to discover circuit bugs using constrained random stimulus. Conclusions

Design and Verification of a Layer-2 MAC Classification Engine for a Gigabit Ethernet Switch ICECS 2010 – Athens, Greece Jorge Tonfat Ricardo Reis Universidade Federal do Rio Grande do Sul (UFRGS) Instituto de Informática - PPGC/PGMicro

Events to not loose

LASCAS 2011 Second IEEE Latin American Symposium on Circuits and Systems February 23-25, 2011 Bogotá, Colombia webpage: lascas.org

IBERCHIP 2011 XVII Iberchip Workshop February 23-25, 2011 Bogotá, Colombia

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CHIP ON THE CLIFFS SBCCI2011 SBMicro2011 August 30 - September 2, 2011 João Pessoa, Brazil

25 CHIP ON THE CLIFFS SBCCI2011 SBMicro2011 August 30 - September 2, 2011 João Pessoa, Brazil

26 CHIP ON THE CLIFFS SBCCI2011 SBMicro2011 August 30 - September 2, 2011 João Pessoa, Brazil

27 BACKUP SLIDES

28 Handshake protocol  Based on request and acknowledge signals

29 Memory Organization  Example using a 4k lookup table:

30 Lookup table organization BitsfieldDescription 71:60VIDVLAN ID associated with MAC address 59:12MAC48-bit MAC address 11:4PORTIDPort associated with MAC address (one-hot encoded) 3RESVReserved 2VALID1: entry is valid, 0: entry is empty 1STATIC1: entry is static - is not to be aged out and it is updated by software, 0: entry is dynamically learned and aged 0AGE1: entry has been accessed or learned since last aging, 0: entry has not been accessed since last aging

31 VLAN memory organization