Reporter: PCLee

Although assertions are a great tool for aiding debugging in the design and implementation verification stages, their use in silicon debug has been limited so far. A set of techniques for debugging with the assertions in either pre-silicon or post- silicon scenarios are discussed. Presented are features such as assertion threading, activity monitors, assertion and cover counters and completion mode assertions. The common goal of these checker enhancements is to provide better and more diversified ways to achieve visibility within the assertion circuits, which, in turn, lead to more efficient circuit debugging. Experimental results show that such modifications can be done with modest checker hardware overhead.

[1]debugging hardware in DUT [3, 10, 11] MBAC: checker generator This paper [6] 4 debugging features: 1.Completion mode assertion 2.Activity monitors 3.Assertion and cover counter 4.Assertion threading [6] 4 debugging features: 1.Completion mode assertion 2.Activity monitors 3.Assertion and cover counter 4.Assertion threading integrate adopt Generate RTL from assertion language

What’s the problem:  Convert high-level assertion language into RTL is difficult.  Enhance assertion checker with several debug features. The proposed method:  MBAC – A tool for transforming PSL or SVA into RTL  Enhance assertion checker by following to increase visibility 。 Completion mode assertion 。 Activity monitors 。 Assertion and cover counter 。 Assertion threading

Dependency graphs:  All signal and parameter dependencies are listed in comment of assertion circuit.  Pinpoint the cause of an error Indicate assertion is complete and not trivially true. Replace asserting when finding error by asserting when finding success. The antecedent must occur. So the consequent determine if the assertion pass or fail.

Observe whether the input stimulus work correctly in a portion of checker. Check when consequent implication never occur, if the antecedent work correctly. If the antecedent never trigger, the antecedent is vacuously true.

Counting failure is straightforward, but counting cover directive require some modification. Cover only trigger at the end of execution. Counter numbers of sequence match

Debugging mechanism for a CPU pipeline. Replicate sequence circuits for failure conditions to isolate from other activations. Allow a violation condition to be separated from the other concurrent activations in the assertion circuit. Example:  5 stage pipeline  Check if memory/register write complete in correct stage.

Metrics:  Number of flip-flips and LUTs  Maximum operating frequency for the worst clk-to-clk path 1. Assertion completion  A little less LUTs than normal mode  A little faster than normal mode 2. Activity monitoring  Maximum operating frequency and FF are virtually not affected  The effect of OR gate is visible 3. Assertion threading  Resource utilisation scales linearly with the number of hardware threads

Author’s conclusion:  This paper presents 4 enhancement debugging method in assertion checker.  They are suitable for complex temporal sequence of assertion language. My conclusion:  The experimental result is lack of reason to explain why the area is small in completion mode.  This paper is about the deep utilization in hardware checker. It is good at discuss the hardware’s correct or error.