U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT Optimizing Compilers CISC 673 Spring 2009 Register Allocation John Cavazos University.

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Presentation transcript:

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT Optimizing Compilers CISC 673 Spring 2009 Register Allocation John Cavazos University of Delaware

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 2 The Memory Hierarchy Higher = smaller, faster, closer to CPU registers L1 cache L2 cache RAM Disk 8 integer, 8 floating-point; 1-cycle latency 8K data & instructions; 2-cycle latency 512K; 7-cycle latency 1GB; 100 cycle latency 40 GB; 38,000,000 cycle latency (!)

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 3 Managing the Memory Hierarchy Programmer view: only two levels of memory Main memory (stores & loads) Disk (file I/O) Two things maintain this abstraction: Hardware Moves data between memory and caches Compiler Moves data between memory and registers

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 4 Overview Introduction Register Allocation Definition History Interference graphs Graph coloring Register spilling

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 5 Register Allocation: Definition Register allocation assigns registers to values Candidate values: Variables Temporaries Large constants When needed, spill registers to memory Important low-level optimization Registers are 2x – 7x faster than cache  Judicious use = big performance improvements

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 6 Register Allocation: Complications Explicit names Unlike all other levels of hierarchy Scarce Small register files (set of all registers) Some reserved by operating system, virtual machine e.g., “FP”, “SP”… Complicated Weird constraints, esp. on CISC architectures For example: Non-orthogonality of instructions

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 7 History As old as intermediate code Used in the original FORTRAN compiler (1950’s) No breakthroughs until 1981! Chaitin invented register allocation scheme based on graph coloring Equivalence first noted by Cocke et al., 1971 Simple heuristic, works well in practice

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 8 Register Allocation Example Consider this program with six variables: a := c + d e := a + b f := e - 1 with the assumption that a and e die after use Variable a can be “reused” after e := a + b Same with variable e  Can allocate a, e, and f all to one register (r 1 ): r 1 := r 2 + r 3 r 1 := r 1 + r 4 r 1 := r 1 - 1

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 9 Basic Register Allocation Idea Value in dead variable not needed for rest of the computation Dead variable can be reused Basic rule: Variables t 1 and t 2 can share same register if at any point in the program at most one of t 1 or t 2 is live !

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 10 Algorithm: Part I Compute live variables for each point: a := b + c d := -a e := d + f f := 2 * e b := d + e e := e - 1 b := f + c {b} {c,e} {b} {c,f} {b,c,e,f} {c,d,e,f} {b,c,f} {c,d,f} {a,c,f}

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 11 Interference Graph Two variables live simultaneously  Cannot be allocated in the same register Construct an interference graph (IG) Node for each variable Undirected edge between t 1 and t 2 If live simultaneously at some point in the program Two variables can be allocated to same register if no edge connects them

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 12 Interference Graph: Example For our example: a f e d c b b and c cannot be in the same register b and d can be in the same register {b,c,f} {a,c,f} {c,d,f} {c,d,e,f} {c,e} {b,c,e,f} {c,f} {b}

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 13 Graph Coloring Graph coloring: assignment of colors to nodes Nodes connected by edge have different colors Graph k-colorable = can be colored with k colors

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 14 Register Allocation Through Graph Coloring In our problem, colors = registers We need to assign colors (registers) to graph nodes (variables) Let k = number of machine registers If the IG is k-colorable, there’s a register assignment that uses no more than k registers

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 15 Graph Coloring Example Consider the example IG a f e d c b There is no coloring with fewer than 4 colors There are 4-colorings of this graph r4r4 r1r1 r2r2 r3r3 r2r2 r3r3

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 16 Graph Coloring Example, Continued Under this coloring the code becomes: r 2 := r 3 + r 4 r 3 := -r 2 r 2 := r 3 + r 1 r 1 := 2 * r 2 r 3 := r 3 + r 2 r 2 := r r 3 := r 1 + r 4

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 17 Computing Graph Colorings How do we compute coloring for IG? NP-hard! For given # of registers, coloring may not exist Solution Use heuristics

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 18 Graph Coloring Algorithm (Chaitin) While G cannot be k-colored While graph G has node N with degree less than k Remove N and its edges from G and push N on a stack S End While If all nodes removed then graph is k-colorable While stack S contains node N Add N to graph G and assign it a color from k colors End While Else graph G cannot be colored with k colors Simplify graph G choosing node N to spill and remove node (spill nodes chosen based number of definitions and uses) End While

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 19 Graph Coloring Heuristic Observation: “degree < k rule” Reduce graph: Pick node N with < k neighbors in IG Eliminate N and its edges from IG If the resulting graph has k-coloring, so does the original graph Why? Let c 1,…,c n be colors assigned to neighbors of t in reduced graph Since n < k, we can pick some color for t different from those of its neighbors

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 20 Graph Coloring Heuristic, Continued Heuristic: Pick node t with fewer than k neighbors Put t on a stack and remove it from the IG Repeat until all nodes have been removed Start assigning colors to nodes on the stack (starting with the last node added) At each step, pick color different from those assigned to already-colored neighbors

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 21 Graph Coloring Example (1) Remove a and then d a f e d c b Stack: {} Start with the IG and with k = 4:

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 22 Graph Coloring Example (2) Now all nodes have fewer than 4 neighbors and can be removed: c, b, e, f f e c b Stack: {d, a}

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 23 Graph Coloring Example (2) Start assigning colors to: f, e, b, c, d, a b a e c r4r4 f r1r1 r2r2 r3r3 r2r2 r3r3 d

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 24 What if the Heuristic Fails? What if during simplification we get to a state where all nodes have k or more neighbors ? Example: try to find a 3-coloring of the IG: a f e d c b

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 25 What if the Heuristic Fails? Remove a and get stuck (as shown below) Pick a node as a candidate for spilling Assume that f is picked f e d c b

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 26 What if the Heuristic Fails? Remove f and continue the simplification Simplification now succeeds: b, d, e, c e d c b

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 27 What if the Heuristic Fails? During assignment phase, we get to the point when we have to assign a color to f Hope: among the 4 neighbors of f, we use less than 3 colors  optimistic coloring f e d c b r3r3 r1r1 r2r2 r3r3 ?

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 28 Spilling Optimistic coloring failed = must spill variable f Allocate memory location as home of f Typically in current stack frame Call this address fa Before each operation that uses f, insert f := load fa After each operation that defines f, insert store f, fa

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 29 Spilling Example New code after spilling f a := b + c d := -a f := load fa e := d + f f := 2 * e store f, fa b := d + e e := e - 1 f := load fa b := f + c

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 30 Recomputing Liveness Information New liveness information after spilling: a := b + c d := -a f := load fa e := d + f f := 2 * e store f, fa b := d + e e := e - 1 f := load fa b := f + c {b} {c,e} {b} {c,f} {b,c,e,f} {c,d,e,f} {b,c,f} {c,d,f} {a,c,f} {c,d,f} {c,f}

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 31 Recomputing Liveness Information New liveness info almost as before, but: f is live only Between f := load fa and the next instruction Between store f, fa and the preceding instruction Spilling reduces the live range of f Reduces its interferences Results in fewer neighbors in IG for f

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 32 Recompute IG After Spilling Remove some edges of spilled node Here, f still interferes only with c and d Resulting IG is 3-colorable a f e d c b

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 33 Spilling, Continued Additional spills might be required before coloring is found Tricky part: deciding what to spill Possible heuristics: Spill variables with most conflicts Spill variables with few definitions and uses Avoid spilling in inner loops All are “correct”

U NIVERSITY OF D ELAWARE C OMPUTER & I NFORMATION S CIENCES D EPARTMENT 34 Conclusion Register allocation: “must have” optimization in most compilers: Intermediate code uses too many temporaries Makes a big difference in performance Graph coloring: Powerful register allocation scheme