Presented By:- Prerna Puri M.Tech(C.S.E.) Cache Coherence Protocols MSI & MESI

Contents Cache and cache coherence Shared cache design advantages MSI WB Protocol State Transition in the MSI Protocol Cache coherence problem MSI example MESI WB Protocol Four states-MESI MESI state transition diagram

Cache and Cache coherence Cache play an important role to Reduce average latency Main memory access costs from 100 to 1000 cycles Caches can reduce latency to few cycles Reduce average bandwidth and demand to access main memory Reduce access to shared bus or interconnect  But private caches create a problem Copies of a variable can be present in multiple caches A write by one processor may NOT become visible to others. Other processors keep accessing old value in their caches

Shared Cache Design: Advantages Cache placement identical to single cache  Only one copy of any cached block  No coherence problem Communication latency is reduced when sharing cache Attractive to Chip Multiprocessors (CMP), latency is few cycles Better utilization of total storage Only one copy of code/data used

MSI Write-Back Invalidate Protocol Three States: Modified: only this cache has a modified valid copy of the block Shared: block is clean and may be cached in more than one cache, memory is up-to-date Invalid: block is invalid Four bus transactions: Bus Read: BusRd on a read miss Bus Read Exclusive: BusRdX Obtain exclusive copy of cache block

Bus Write-Back: BusWB on replacement Flush on BusRd or BusRdX Cache puts data block on the bus in lieu of memory Cache-to-cache transfer and memory is updated Cont..

State Transitions in the MSI Protocol Processor Read Cache miss  causes a Bus Read Cache hit (S or M)  no bus activity Processor Write Generates a BusRdX when not Modified BusRdX causes other caches to invalidate No bus activity when Modified block Observing a Bus Read If Modified, flush block on bus Picked by memory and requesting cache Block is now shared Observing a Bus Read Exclusive Invalidate block Flush data on bus if block is modified M I S PrRd/— PrWr/— PrRd/BusRd PrWr/BusRdX PrRd/— BusRd/— BusRd/Flush BusRdX/Flush Replace/BusWB BusRdX/— Replace/—

The Cache Coherence Problem Processors see different values for u after event 3 With write back caches value written back to memory depends on which cache flushes or writes back value when processes accessing main memory may see very old value Unacceptable to programs

MSI Example P1 Cache P2P3 Bus Cache MEMORY BusRd Processor Action State in P1 State in P2State in P3Bus TransactionData Supplier S --- BusRdMemory P1 reads X X=10 S

P1 Cache P2P3 Bus Cache MEMORY X=10S Processor Action State in P1 State in P2State in P3Bus TransactionData Supplier S --- BusRdMemory P1 reads X P3 reads X BusRd X=10S S ---SBusRdMemory X=10

P1 Cache P2P3 Bus Cache MEMORY X=10S Processor Action State in P1 State in P2State in P3Bus TransactionData Supplier S --- BusRdMemory P1 reads X P3 reads X X=10 S S ---SBusRdMemory P3 writes X BusRdX ---I M I MBusRdX X=10 X=-25

P1 Cache P2P3 Bus Cache MEMORY Processor Action State in P1 State in P2State in P3Bus TransactionData Supplier S --- BusRdMemory P1 reads X P3 reads X X=-25M S ---SBusRdMemory P3 writes X ---I I MBusRdX P1 reads X BusRd X=-25 S S S ---SBusRdP3 Cache X=10X=-25

MESI Write-Back Invalidation Protocol To reduce two types of unnecessary bus transactions BusRdX that snoops and converts the block from S to M when only you are the sole owner of the block BusRd that gets the line in S state when there is no sharers (that lead to the overhead above) Introduce the Exclusive state One can write to the copy without generating BusRdX Illinois Protocol: Proposed by Pamarcos and Patel in 1984 Employed in Intel, PowerPC, MIPS

Four States: MESI M: Modified Only this cache has copy and is modified Main memory copy is stale E: Exclusive or exclusive-clean Only this cache has copy which is not modified Main memory is up-to-date S: Shared More than one cache may have copies, which are not modified Main memory is up-to-date I: Invalid

MESI State Transition Diagram Processor Read Causes a BusRd on a read miss BusRd(S) => shared line asserted Valid copy in another cache Goto state S BusRd(~S) => shared line not asserted No cache has this block Goto state E No bus transaction on a read hit PrWr/— PrRd/— E M I S PrRd PrRd/ BusRd(S) BusRdX/ Flush BusRd/— PrWr/ BusUpgr PrWr/ BusRdX BusRd/ Flush BusRdX or BusUpgr/— BusRdX/— PrRd/— BusRd/— PrRd/ BusRd(~S) PrWr/— Replace/ BusWB Replace/—

Processor Write Promotes block to state M Causes BusRdX / BusUpgr for states I / S To invalidate other copies No bus transaction for states E and M Cont..

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