TECH 6 VLIW Architectures {Very Long Instruction Word}

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Presentation transcript:

TECH 6 VLIW Architectures {Very Long Instruction Word} {EPIC: Explicit Parallel Instruction-set Computer} {CISC  RISC EPIC} 6.1 Basic principles 6.2 Overview of proposed and commercial VLIW architectures 6.3 Case study: The Trace 200 family TECH Computer Science CH01

Basic Structure of VLIW Architecture

Basic principle of VLIW Controlled by very long instruction words comprising a control field for each of the execution units Length of instruction depends on the number of execution units (5-30 EU) the code lengths required for controlling each EU (16-32 bits) 256 to 1024 bits Disadvantages: on average only some of the control fields will actually be used waste memory space and memory bandwidth e.g. Fortran code is 3 times larger for VLIW (Trace processor)

Instruction word format: Trace 7/200

VLIW: Static Scheduling of instructions/ Instruction scheduling done entirely by [software] compiler Lesser Hardware complexity translate to increase the clock rate raise the degree of parallelism (more EU); {Can this be utilized?} Higher Software (compiler) complexity compiler needs to aware hardware detail number of EU, their latencies, repetition rates, memory load-use delay, and so on cache misses: compiler has to take into account worst-case delay value this hardware dependency restricts the use of the same compiler for a family of VLIW processors

6.2 overview of proposed and commercial VLIW architectures

6.3 Case study: Trace 200

Trace 7/200 256-bit VLIW words Capable of executing 7 instructions/cycle 4 integer operations 2 FP 1 Conditional branch Found that every 5th to 8th operation on average is a conditional branch Use sophisticated branching scheme: multi-way branching capability executing multi-paths assign priority code corresponds to its relative order

Trace 28/200: storing long instructions 1024 bit per instruction a number of 32-bit fields maybe empty Storing scheme to save space 32-bit mask indicating each sub-field is empty or not followed by all sub-fields that are not empty resulting still 3 time larger memory space required to store Fortran code (vs. VAX object code) very complex hardware for cache fill and refill Performance data is Impressive indeed!

Trace: Performance data

Transmeta: Crusoe Full x86-compatible: by dynamic code translation High performance: 700MHz in mobile platforms

Crusoe “Remarkably low power consumption” “A full day of web browsing on a single battery charge” (333-400Mhz TM3120 in production now, running Linux! TM5400 runs Windows, production mid 2000) Playing DVD: Conventional? 105 C vs. Crusoe: 48 C

Intel: Itanium (VLIW) {EPIC} Processor