CprE 211 Break-out Board Layout

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Presentation transcript:

CprE 211 Break-out Board Layout Address Bus (A23-A0) #1 A5-A2 1 MB SRAM (#1) 1 MB SRAM (#2) 1 MB SRAM (#3) 1 MB SRAM (#4) #2 CS0* #3 CS1* Address Demux D31-D24 D23-D16 D15-D8 D7-D0 #4 To Enable Lines for each Buffer or Latch Digital Input 1 Digital Input 2 DIP Switch 1 DIP Switch 2 Potentiometers Input Devices Analog 1 Analog 2 Pull-Down Resistors Pull-Down Resistors Optoisolator Optoisolator Keyboard Input Analog 3 Analog 4 D7-D0 Octal Latch Octal Latch Octal Latch Octal Latch Octal Latch AN0 AN1 AN2 AN3 Data Bus (D31-D0) 7-Segment Disp. 7-Segment Disp. LED Bargraph 1 LED Bargraph 2 8-bit Output Pins 8-bit Output Pins Output Devices Data Strobe Resistor Bank Resistor Bank LCD Display Resistor Bank Resistor Bank Optoisolator Optoisolator 7-Seg Decoder 7-Seg Decoder External 7-Seg Display (also on board) Octal Buffer Octal Buffer Octal Buffer Octal Buffer Octal Buffer Octal Buffer 8-bit Input Port D7-D0 Resistor Bank 7-Segment Disp.

Address Selection for External Devices !CS2 A05 A04 5 V 5 V Strobe Vcc A03 Pin 1 Pin 24 A Inhibit A02 B C S7 D S6 S10 Device 10 Enable S5 S11 Device 11 Enable S4 74HC4514 S8 Device 8 Enable S3 S9 Device 9 Enable S1 S14 Device 14 Enable S2 S15 Device 15 Enable S0 S12 Device 12 Enable Gnd S13 Device 13 Enable Device 0 Enable Device 2 Enable Address Bus Device 1 Enable Device 3 Enable Device 4 Enable Device 5 Enable Device 6 Enable Device 7 Enable

7 – Segment Decoder and Display 5 V Pin 8 5 V Output 5 D05 A1 Vcc D06 Pin 1 Pin 16 Output 6 A2 f P0 P15 Pin 9 Pin 1 Pin 16 !LE g P1 P14 Pin 10 !RBO a P2 P13 Pin 7 DM9368N !RBI b P3 270 W Resistor Network (8) P12 Pin 6 D07 Output 7 A3 c P4 P11 Pin 4 D04 Output 4 A0 d P5 P10 Pin 2 Gnd e P6 P9 Pin 1 NC P7 P8 NC 5 V Pin 8 5 V D02 Output 2 A1 P15 D03 Pin 1 Pin 16 Output 3 A2 f P0 P15 Pin 9 Pin 1 Pin 16 !LE g P1 P14 Pin 10 !RBO a P2 P13 Pin 7 !RBI DM9368N b P3 270 W Resistor Network (8) P12 Pin 6 D01 Output 1 A3 c P4 P11 Pin 4 D00 Output 0 A0 d P5 P10 Pin 2 Gnd e P6 P9 Pin 1 NC P7 P8 NC

Octal Buffer for Output Devices Device x Enable Line from Address Selection 5 V !OE1 Vcc D0 Pin 1 Pin 20 A1 !OE2 D1 A2 Y1 Output 0 D2 A3 Y2 Output 1 D3 A4 Y3 Output 2 D4 SN74AHCT541 A5 Y4 Output 3 D5 A6 Y5 Output 4 D6 A7 Y6 Output 5 D7 A8 Y7 Output 6 Gnd Y8 Output 7 Data Bus

Octal Latch for Input Devices !OE Vcc Pin 1 Pin 20 D0 Input 0 D0 O0 Input 1 D1 O1 D1 D2 O2 D2 Input 2 D3 O3 D3 Input 3 SN74AHCT541 Input 4 D4 O4 D4 D5 O5 D5 Input 5 Input 6 D6 O6 D6 D7 Input 7 D7 O7 Gnd LE Device x Enable Line from Address Selection Data Bus

LED Bargraph Output (2 total) 5 V Pin 1 Output 0 P0 P15 Output 1 P1 Pin 1 Pin 16 P14 Output 2 P2 P13 Output 3 P3 270 W Resistor Network (8) P12 Output 4 P4 P11 Output 5 P5 P10 Output 6 P6 P9 Output 7 P7 P8

DIP Switch Input (2 total) 5 V Gnd P0 P15 Pin 1 Pin 16 P1 P14 P2 P13 P3 10 KW Resistor Network (8) P12 P4 P11 P5 P10 P6 P9 P7 P8 Input 0 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7

Data Bus (D32-D0) Address Bus (A23-A0) PB-0555 Board To Enable Lines Pin 1 Pin 20 P0 P15 P1 P18 Pin 1 Pin 16 P1 P14 P2 P17 P2 P13 P3 P16 5 V P3 P12 P4 P15 16 Pin 20 Pin P4 P11 P5 P14 P5 P10 P6 P13 P6 P9 P7 P12 P7 P8 P8 P11 P9 P10 Data Bus (D32-D0) PB-0555 Board I/O Pin Header #1 To Enable Lines for each Buffer Or Latch I/O Pin Header #2 PPC555 P0 P23 I/O Pin Header #4 Pin 1 Pin 24 P1 P22 P2 P21 Address Bus (A23-A0) P3 P20 I/O Pin Header #3 P4 P19 Address Selection P5 P18 24 Pin P6 P17 I/O Pin Header #1 P7 P16 I/O Pin Header #2 I/O Pin Header #4 P8 P15 I/O Pin Header #3 P9 P14 P10 P13 P11 P12