1 LW 6 Week 6 February 26, 2015 UCONN ECE 4211 F. Jain Review of BJT parameters and Circuit Model HBT BJT Design February 26, 2015 LW5-2 PowerPoint two.

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1 LW 6 Week 6 February 26, 2015 UCONN ECE 4211 F. Jain Review of BJT parameters and Circuit Model HBT BJT Design February 26, 2015 LW5-2 PowerPoint two lectures

BJT parameters 2

Common emitter P-n-p BJT: Current relationships 3 I CN is also referred as I CBO, i.e. the reverse current flowing when I E =0 (in common base). (50) (46) (51)

Circuit model, p.239 4

Circuit model, p.240 5

HBT Eqb. p.241 6

HBT Biased. p.242 7

3B. 6 Design of a Bipolar Junction Transistor Figure 5. Cross-section and Top view of a n-p-n transistor 8 Design specifications: Design an n-p-n transistor with a common emitter gain,  o = 500. The device cross- section and a typical layout is given in Fig. 5. The cut-off frequency f a =    value in GHz is also provided. Starting substrate is an epitaxial wafer with a 10 Ohm-cm n-Si epitaxial layer on p-Si substrate. Epi thickness is not known. Given for guideline purposes are the following device parameters:

3B. 6 Design of a Bipolar Junction Transistor 9

10 Step (b) Estimate base-emitter and base-collector capacitances under zero bias and biased conditions.

11 Step (e) Selection of : Isolation region width and size Separation between buried layer and isolation diffusion and other features Collector contact diffusion as you may seem fit (i.e. deep plug going to the buried layer or like emitter diffusion) Buried layer parameters Using diffusion coefficients as obtained during the diffusion experiments. List the process data needed in the fabrication of the transistor.  C = Collector capacitance charging time  r sc C TE r sc = collector resistance, C TE = collector capacitance Q. 3. BJT Design Problem: Equivalent to one home work set. You can substitute it for any missed homework or any bad grade in a home work set. Design an n-p-n bipolar junction transistor with a common emitter gain,  o = 500. The device cross-section and a typical layout are given in Figure 3. Provide: (a) doping levels of emitter, base, and collector, (b) width of the base, (c) determine the cut-off frequencies f   and f   and (d) How would you increase cut-off frequency by a factor of 100 or 1000; what parameter(s) would you vary. Name the most important parameter for a given device size. Given: Starting substrate is an epitaxial wafer with a 10 Ohm-cm n-Si epitaxial layer on p-Si substrate. Epi thickness is not known you have to find it from base width W used in your design.. Given for guideline purposes are the following device parameters: Emitter:Base: D p,E =20 cm 2 /sec.D n,B =40 cm 2 /sec (diffusion coefficient for electrons)  p =10  sec (lifetime of holes injected from base)  n =2  sec (electrons injected from the emitter) Emitter area A EB = 2  m x 2  mBase-collector area A BC = 6  m x 6  m Emitter-collector voltage V CE = 5 Volts

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