Lecture 8  make

Overview: Development process  Creation of source files (.c,.h,.cpp)  Compilation (e.g. *.c  *.o) and linking  Running and testing programs

d.h d.cpp d.bj Object files contain machine code but not in executable form. Object files contain references (calls) to external functions that must be resolved. Linker programs are commonly invoked by (C/C++) compilers Separate Compilation Steps – Step 1 source files compiled to object files – Step 2 objects files linked to form executable file.exe a.h a.cpp a.obj b.h b.cpp b.obj c.hc.cpp c.obj A change in one module (requires only 1 recompile:

Development tools in UNIX  Compilation (e.g. *.c *.o) and linking Compilers (e.g. gcc, g++ ) Compilers (e.g. gcc, g++ ) Automatic building tools (e.g. make ) Automatic building tools (e.g. make )  Running and testing programs Debuggers (e.g. gdb ) Debuggers (e.g. gdb )  Integrated development environments (IDEs)

Compiling with g++  GNU C++ compiler  Performs one or more of the following: C++ pre-processing C++ pre-processing Compilation Compilation Linking Linking

g++ Examples  g++ hello.cpp (compile hello.cpp, produce executable a.out )  g++ -o hello hello.cpp other_fns.cpp (compile hello.cpp and other_fns.cpp, produce executable hello )  From any source file, you can produce an object file to be linked in later to an executable g++ -c hello.cpp g++ -c other_functions.cpp g++ -o hello hello.o other_functions.o

Using make in compilation  With medium to large software projects containing many files, it’s difficult to: Type commands to compile all the files correctly each time Type commands to compile all the files correctly each time Keep track of which files have been changed Keep track of which files have been changed Keep track of files’ dependencies on other files Keep track of files’ dependencies on other files  The make utility automates this process

Basic Makefile Example program : main.o iodat.o dorun.o g++ -o program main.o iodat.o dorun.o main.o : main.cpp g++ -c main.cpp iodat.o : iodat.cpp g++ -c iodat.cpp dorun.o : dorun.cpp g++ -c dorun.cpp

How make works  Reads a file called [Mm]akefile, which contains rules for building a “target”  If the target depends on a file, then that file is built If that file depends on a third file, then the third file is built, and so on… If that file depends on a third file, then the third file is built, and so on… Works backward through the chain of dependencies Works backward through the chain of dependencies  Targets only built if they are older than the files they depend on

Types of lines in Makefiles  Dependency or rules lines  Commands  Macro assignments  Comments

Dependency/rules lines  Specify a target and a list of prerequisites (optional) for that target target : prereq1 prereq2 prereq3 …

Command lines  Follow dependency lines  MUST start with a TAB!  Any command that can be run in the shell can be placed here target : prereq1 prereq2 command1command2  Special variables in commands: represents the target represents the target $? represents prereqs that are newer than target $? represents prereqs that are newer than target

Simplified Makefile example program : main.o iodat.o dorun.o g++ -o main.o iodat.o dorun.o main.o : main.cc g++ -c $? iodat.o : iodat.cc g++ -c $? dorun.o : $? g++ -c dorun.cc

Macro (variable) assignments  You can use macros to represent text in a Makefile Saves typing Saves typing Allows you to easily change the action of the Makefile Allows you to easily change the action of the Makefile  Assignment: MACRONAME = macro value  Usage: ${MACRONAME}

Simplified Example Makefile with macros OBJS = main.o iodat.o dorun.o CC = /usr/bin/g++ program : ${OBJS} ${CC} -o ${OBJS} main.o : main.cpp ${CC} -c $? iodat.o : iodat.cpp ${CC} -c $? ${CC} -c $? dorun.o : dorun.cpp ${CC} -c $? ${CC} -c $?

Comments and other Makefile notes  Comments begin with a ‘#’  Lines that are too long can be continued on the next line by placing a ‘\’ at the end of the first line

Invoking make  Be sure that your description file: is called makefile or Makefile is called makefile or Makefile is in the directory with the source files (to simplify) is in the directory with the source files (to simplify)  make (builds the first target in the file)  make target(s) (builds target(s))  Important options: -n : don’t run the commands, just list them -n : don’t run the commands, just list them -f file : use file instead of [Mm]akefile -f file : use file instead of [Mm]akefile

The Searching Order of make  GNUmakefile  makefile  Makefile

Other useful Makefile tips  Include a way to clean up your mess: %make clean No dependencies! No dependencies!clean: /bin/rm -f *.o core

Makefile example b : c d rm echo $? > a : c rm echo $? > target : a b rm echo $? > cat $? >> all : a b c d target start : rm `ls | egrep –v ‘\ ’` ; echo D > d ; echo C > c echo B > b ; echo A > a ; echo Target > target