555 Timer ©Paul Godin Updated February 2008

Oscillators ◊We have looked at simple oscillator designs using an inverter, and had a brief look at crystal oscillators. ◊In this presentation, we introduce the 555 timer; a versatile device that is easier to calculate, design and configure in a variety of ways

A Versatile Device ◊The 555 Timer is one of the best known IC’s. ◊The 555 is part of every experimenter's tool kit ◊Capable of creating a wide variety of circuits, including: ◊Oscillators with adjustable frequency and Duty Cycle ◊Monostable Multivibrators ◊Analog to digital Converters ◊Frequency Meters ◊Many other applications…. ◊The clock on the Vulcan Board is generated by a 555 timer

555 Timer Configurations ◊We will look at the 555 timer in 2 modes: ◊Astable ◊With some calculations, we can determine the values of the capacitor and the 2 resistors (Ra and Rb) for astable operations. ◊Monostable ◊We can determine the value of the resistor and the capacitor with a simple formula for one-shot operations. ◊There are many other configurations and applications for this device

555 Layout Also available: 556 (two-555’s in one DIP package) 555 in a “metal can” configuration Ground Trigger Output Reset Vcc Discharge Threshold Control Ground Trigger Output Reset Vcc Discharge Threshold Control

Operation of the 555 Timer Astable Multivibrator 555.6

Oscillator Configuration ◊Externally, the 555 requires an RC circuit to create the time delays required for the time high and the time low. ◊Standard configuration requires ◊common capacitor ◊a resistor for the charge cycle ◊a resistor for the discharge cycle 555.7

General Configuration ◊Basic connections: ◊Ground ◊Vcc ◊Note: some 555 timers may function at voltages other than 5 volts. ◊Reset (active low) ◊Output Ground Trigger Output Reset Vcc Discharge Threshold Control

General Configuration ◊Specialized connections: ◊Trigger ◊monitors low voltage ◊Threshold ◊monitors high voltage ◊Discharge ◊path to ground, to discharge the capacitor ◊Control ◊specialized input ◊filtering ◊special applications Ground Trigger Output Reset Vcc Discharge Threshold Control

Astable Configuration #1 (“Standard” Configuration) Ground Trigger Output Reset Vcc Discharge Threshold Control Vcc Ra Rb C Vcc

Astable Filter Cap 0.01μF Calculated Values Note: Duty Cycle must be > 50%

Astable Configuration #1 (“Standard” Configuration) Minimum duty cycle > 50%

Calculations: Astable THTH TLTL Notes: The value is a factor associated with the charge/discharge cycle of the 555 timer. Duty Cycle must be > 50% Time High, Time Low Set

Sample Calculation ◊Design an oscillator with a frequency of 200Hz with a duty cycle of 78%. 1.Determine Period (T): 2.Determine T H and T L : Time High, Time Low Set

Since there are 2 variables in the T L equation, select C: 4.Determine R B by using the T L equation: C=10μF Sample Calculation Time High, Time Low Set

Determine the value for R A : Sample Calculation Time High, Time Low Set

Calculations: Astable Notes: The value is a factor associated with the charge/discharge cycle of the 555 timer. Duty Cycle must be > 50% Frequency, Duty Cycle Set

Sample Design ◊Build an oscillator using a 555 timer with a frequency of 72kHz at 75% D.C. Use a 100F capacitor. Frequency, Duty Cycle Set

Design Solution 1- Determine the ratio of the resistors Ra and Rb: 2- Use the ratio in the frequency equation (substitution): Frequency, Duty Cycle Set

Design Solution 3- Solve for Rb: 4-Solve for Ra: 5-Use standard values (optional step): Ra=100k Rb=47k Frequency, Duty Cycle Set

Design Solution 6- Calculate actual frequency and DC: Frequency, Duty Cycle Set

Design Solution 7- Create the circuit diagram using EWB: 555 Timer, 75.7% D.C. Frequency, Duty Cycle Set

Minimum Value for Ra ◊The discharge transistor causes the capacitor to discharge to ground. ◊Ra must have a minimum value of 25 to prevent a short circuit of the power supply through the discharge transistor. Minimum Value

OTHER ASTABLE CONFIGURATIONS

Astable Configuration#2 Rb must be <.5 Ra

Astable Configuration #

Specification sheet ◊From the specification sheet for the LM555, discuss the following: ◊Operational voltage range ◊Maximum current output for each state ◊Frequency Range ◊Output rise and fall time What is a disadvantage of the 555 as a timing device?

555 as a Monostable ◊The 555 timer can also be configured as a monostable. ◊The 555 Monostable has interesting characteristics that may be used in specific applications. 555mono.28

Timing Diagram Tw The Trigger is active low, not edge triggered. Input trigger Output pulse Output pulse created when input trigger voltage is less than 1/3 Vcc If the trigger is held low beyond calculated pulse width, the output pulse follows the input trigger 555mono.29

Monostable Filter Cap 0.01μF Calculated Values 555mono.30

Calculations: Monostable Notes: The value 1.1 is a k-factor associated with the 555 timer. The trigger is active-low (not edge-triggered), and must be brought high before the end of the pulse width. Tw 555mono.31

Sample Monostable Calculation ◊Design a Monostable that produces a 5S pulse. Use a 100F capacitor. 555mono.32

Animated Slide The following slides contain animations to demonstrate the operations of: 555 as a monostable 555mono.33

Monostable 0 + < Vc Wait-state. The transistor discharges the Capacitor 0 A low is applied to the trigger input. The comparator provides a logic high; the latch is set > - 1 Q’ goes low; Q high. The transistor is “off”. Cap charges. +> - Capacitor voltage > 2/3 Vcc. High comparator output high. 1 Latch reset. Q’ logic high. Capacitor discharges, waits. 1 0 Animated 555mono.34

Animated Slides The following slides contain animations to demonstrate the operations of: 555 as an astable: charge cycle 555 as an astable: discharge cycle

555.36

+ < < + 1 Vc 0 1 Animated charge cycle + > > Capacitor Charges via Ra and Rb Latch in a set state Q’ is low; Q output is high Capacitor continues to charge Lower comparator provides logic low. Latch in hold state. Upper comparator + input is greater than 2/3 Vcc reference Latch receives a reset state Q’ is high; Q output is low Transistor is “on” and a connection to ground is made. Capacitor begins to discharge

Vc < - - < + Animated discharge cycle > > + 1 Capacitor is discharging. Q output is low. Upper comparator + voltage less than reference voltage. Latch in a hold state. Lower comparator + voltage is greater than – voltage. Latch is set. Q’ is low. Q output is high. Transistor is “off”. Capacitor begins to charge

©Paul R. Godin prgodin gmail.com END