TCU STATUS A.Di Cicco, M.Della Pietra, G.Fiorillo,P.Parascandolo Adele DI CICCONapoli, 27 Novembre 2003

2 Flow Chart PMT Trigger condition logic Global trigger request Local trigger request Global drift or busy? Acquire all crates No trigger Acquire only fired pixels Local drift or busy? PMT-pixels coincidences logic Pixels Majority/Pattern logic PMT local trigger request? Wire planes coincidence Logic (pixel fired) No Trigger request AWS Discriminator LTCU - PMTAWS - LTCU Discriminator TCU TS PMT Adele DI CICCONapoli, 27 Novembre 2003

3 GLOBAL/LOCAL trigger BUSY logic After validation of a global trigger request TS gives the GLOBAL_DRIFT signal to all v789 boards During a GLOBAL_DRIFT, TS doesnt accept any other trigger request, while, during a GLOBAL_BUSY (DAQ dead time for acquisition data download from all chambers) it accepts only a Local Trigger request During LOCAL_DRIFT it doesnt accept any other trigger request in the same crate

4 Trigger classification depends on: Energy deposition/number of PMT fired. Detector occupancy 2D/3D Pattern of fired pixels TS gives GLOBAL trigger when a MAJORITY condition is met in PMT logic Otherwise the wires define trigger locality TS GLOBAL/LOCAL Logic Adele DI CICCONapoli, 27 Novembre 2003

5 T600 pixel definition Pixel fired 1 pixel area: ~ 0.6 m 2 Total Number of Pixels ~ 80 1 pixel area: ~ 0.14 m 2 Total Number of Pixels ~ cm28.8 cm 9.6 cm 1 pixel area: ~ m 2 Total Number of Pixels ~ x 3 Induction II wires 32 x 3 Collection wires 32 Collection wires 32 Induction II wires 32x9 Collection wires 32x9 Induction II wires

6 TCU FEATURES 1 boards per chamber (depending on segmentation) VME standard Each TCU module receives as input –N aws signals from the 20 AWS-LTCU boards of a chamber N aws =40 if sectors are made of 32x9 wires N aws =120 if 32x3 wires N aws =360 if 32 wires –N pmt signals from PMT-LTCU –N ext from external (spectro, beam,...) checks Majority, 2D/3D Pattern logic conditions event is labelled according to topology TCU performs coincidences between: The wire planes (in a 3 s time windows) PMT signals External requests Adele DI CICCONapoli, 27 Novembre 2003

7 Pixel detection (using only two coordinates) 3 s IND2 IND2 streched Collection Pixel

8 PMT Induction II signal Collection signal LTCU T 1 signal LTCU T 2 signal TCU Trigger request TS Trigger signal T 3 s T 1.5 ms Trigger dead time n-bit Time Diagram (with PMT signal)

9 PMT Induction II signal Collection signal LTCU T 1 signal LTCU T 2 signal TCU Trigger request TS Trigger signal T 3 s T 1.5 ms Trigger dead time n-bit

10 Induction II signal Collection signal LTCU T 1 signal LTCU T 2 signal First level TCU Trigger request TS Trigger signal T 3 s T 1.5 ms n-bit Time Diagram Second level TCU Trigger request

11 It is necessary to store the evolution in time of the number of fired pixel For a long track consecutive pixels will be fired (in different time) according to the track direction. In this case the event is global but we could acquire it as many local events. In case of Supernova burst several pixels could be fired with a big spacing in position and in time. Pattern Recognition It is necessary to make consecutive pictures to store detectors activity

12 Rack 11Rack 13 General Idea on Partial majority Window runs on the detector Majority condition is checked for each window Adele DI CICCONapoli, 27 Novembre 2003

13 General scheme TCU IND2[12:0] FPGA1 WIRES Coincidences FPGA2 WIRES Coincidences FPGA3 WIRES Coincidences MAJ PMT FPGA Xilinx Spartan PMT signal COLL[8:0] IND2[12:0] COLL[8:0] IND2[12:0] VME INTERFACE Xilinx Spartan Address Data S_OUT DIAG LOAD EM FORCE CS[3:0] SEL[2:0] CS2CS1 CS0 CS3 Adele DI CICCONapoli, 27 Novembre 2003

14 Wire Coincidences FPGA Features The detector is subdivided in three (or more) sections Each section is monitored by a different WC-FPGA Each WC-FPGA Makes coincidences between wires of different directions Checks the occupancy of the section Detects spots, tracks,... Adele DI CICCONapoli, 27 Novembre 2003

15 receives an N bit Word which defines PMT status makes concidences between PMT and wires makes global trigger proposals PMT FPGA Features VME interface Features is directly interfaced to VME CPU and it establishes communication between VME and the rest of the board. Adele DI CICCONapoli, 27 Novembre 2003

16 Total Majority ACCUMULATOR Adele DI CICCONapoli, 27 Novembre R

17 Wire Coincidences FPGA preliminary SYNC BLK SYNC BLK AND BLK 9 13 INA INB MASK 9 13 MASK 9 AA BB 13 A0_B[4:0] A1_B[5:1] A2_B[6:2] A3_B[7:3] A4_B[8:4] A5_B[9:5] A6_B[10:6] A7_B[11:7] A8_B[12:8] FLASH ADR[4:0] ENC REG_A REG_B REG_C SUM BLK VTH Internal Xilinx Memory Whole Carpet Majority ENCA ENCA2 ENCA3 MJLOCAL MJGLOBAL ADDRESS GENERATOR FLASH CLK PIPELINE

18 Blocks description SYNC BLK SYNC BLK syncronizes the data and makes a picture of the detector when FLASH signal occours AND_BLK AND_BLK makes coicidences between fired wires ADDRESS GENERATOR ADDRESS GENERATOR produces the address for Multiplexer to select the sector ENC ENC sums pixel inside the sector REG_A, REG_B, REG_C REG_A, REG_B, REG_C store three adjacent sectors SUM SUM sums pixels from adjacent sectors Adele DI CICCONapoli, 27 Novembre 2003

19 R R R R R R R R R W W W W Ambiguous pixels W wrong pixel R right pixel Nature of detector introduces ambiguity Adele DI CICCONapoli, 27 Novembre 2003 R R W W R W R W W

20 Rack 11Rack 13 Possible solutions Higher segmentation In this case LTCU will produce a FAST OR from a smaller number of boards TCU will have more input signals Possibility to send trigger to single board in the crate Use of Induction1 plane Adele DI CICCONapoli, 27 Novembre 2003

21 R R R W W W R R R W W W W W Third plane use Adele DI CICCONapoli, 27 Novembre 2003

22 2nd level trigger Possibility to have a two levels trigger: Every time a trigger condition is met the TCU produces a 1° level trigger and sends the proposal to the Supervisor The TCU records the plane pictures before and after the event and performs a topological analysis in order to define locality/globality and type of event. It produces a second level trigger. Adele DI CICCONapoli, 27 Novembre 2003

23 Uniboard (Parascandolo,Masone) ICC MASTER ICC SLAVE1 ICC SLAVE2 ICC SLAVE3 Spartan II FAUX Spartan II VME (J2) Spartan II VME (J1) Spartan II 333 Adele DI CICCONapoli, 27 Novembre 2003 FIFO A FIFO B FIFO A FIFO B FIFO A FIFO B FIFO A FIFO B 18 FF EF

24 UNIBOARD VME INTERFACE Xilinx Spartan XC2S100 INPUT STAGE Xilinx Spartan XC2S100 SYNCHRONOUS FIFO IDT72V programmable input / output

25 Conclusions We are working to define algorithms to perform a topological analisys of event in order to define locality and globality of event We are studing the possibility to use the third coordinate We are evaluating the possibility to have higher segmentation and two trigger level.