Computer ArchitectureFall 2007 © October 31, CS-447– Computer Architecture M,W 10-11:20am Lecture 17 Review

Computer ArchitectureFall 2007 © New Material Covered Datapath and Control: Datapath - Arithmetic Logic Unit (ALU) - Register File (RF) Control - Finite State Machines Single Cycle Datapath: Stages in the Datapath - Fetch - Decode and Register Fetch - Arithmetic/Logic Execution - Memory - Write Back - PC Update: Default versus Branch Single Cycle Datapath (con’t): Instructions through the Pipeline - R-Type Instructions - I-Type Instructions - Load/Store Instructions - Branch Instructions Disadvantages of a Single Cycle Processor - Instructions have to go through all stages - Slowest instruction dictates speed - Only a small portion of the datapath is active at a given time Multi-Cycle Datapath: 5 stages (IF, ID, EX, MEM, WB) Some instructions “skip” irrelevant stages  saves execution time

Computer ArchitectureFall 2007 © New Material Covered (con’t) Pipelining: Each clock cycle, the instruction completes a “partial” execution through one of the stages (IF, ID, EX, M, WB). Structural Hazards Control Hazards Data Hazards Resolving Hazards via - Stalling - Forwarding - Latency, versus Throughput The Effect of Pipelining on CPI: Clock Cycle Time Execution Time (and Speedup) Consumed Energy Modern CPU: Superpipelining Parallel Pipelining Diversified Pipelining Dynamic Pipelining Modern Processors Employ Diversified Pipelines Out of Order Execution Dynamic Scheduling