Presenter: PCLee Design Automation Conference, ASP-DAC '07. Asia and South Pacific

In this paper, we present a method for generating checker circuits from sequential-extended regular expressions(SEREs). Such sequences form the core of increasingly-used Assertion-Based Verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion and length matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.

Efficient Automata- Based Assertion- Checker Synthesis of SEREs for Hardware Emulation Efficient Automata-Based Assertion-Checker Synthesis of PSL properties Assertion Checkers – Enablers of Quality Design

[2]: basic framework of MBAC [1],[3]: IBM’s FoCs [4],[6],[7],[8]: converting regular expression to hardware [5]: hardware compiler [9],[10]: check property during simulation [11]: removing ε transition, minimizing and determinization classical automata Compare [1],[3] with MBAC This paper [4],[6],[7],[8] is a start point of sequence transforming [5] [9],[10] is not a dynamic trace Add implementatio n of SERE to [2] Add boolean nature to [11]

Problem: 1. Assertions are usually expressed at higher levels of abstraction that are not easily expressed in a Hardware Description Language (HDL). 2. The symbols in sequences correspond to many simultaneously interacting Boolean expressions, as opposed to the plain symbols used in pattern matching. 3. The notion of sequence intersection is often not treated in regular expression matching. 4. Automata-based regular expression recognizers only require the matching of patterns, assertions often require explicit detection of sequence failures. 5. Sequence fusion is required in assertions sequences. Presented method:  MBAC checker generator tool is used to generate resource efficient assertion checker circuits.  This paper presented algorithm for sequence fusion and length- matching, and also develop an algorithm for generating failure detection automata.

Conditional mode: Sub-statement semantic context for which the detection of a sequence must be performed. For each start condition, the result signal is triggered each and every time the chain of events described by the sequence is observed. It can be used to describe the desired behavior. Obligation mode: Semantic context for which the failure of a sequence must be identified. For each start condition, if the chain of events described by the sequence does not occur, the result signal is triggered (for a given start condition, the first and only the first failure is identified). It can be used to detect first error. always ({b1 ; b2} |-> {b3 ; b4})

Symbol encoding differs from conventional regular expressions because in SEREs, the alphabet Σ(a non-empty finite set) represents arbitrary Boolean expressions. Symbol encoding of expression:  One symbol is received at each step, while the Boolean expression symbol encoding causes multiple symbols to be received at each step. Symbol encoding of sequence:  Encoding of Boolean primitives to s-automaton symbols is to assign a distinct symbol si to each Boolean primitive bi, without concern for the fact that two Boolean primitives may simultaneously evaluate to true. It is possible to create a symbol encoding which represents the power set of the Boolean primitives.  However, when a SERE references many Boolean primitives, the exponential increase of symbols and edges quickly becomes impractical.

Sequence automata construction use the recursively construction technique. Conventional regular expression operator:  Conventional regular expression operators are concatenation(;), choice(|) and kleen star(*).  The boolean expression encoding scheme produces nondeterministic automata because from a given state, two distinct symbols can cause simultaneous outgoing transitions when their respective Boolean expressions are both true.  This can be reused for sequence automata.

Length-Matching Intersection:  Length-Matching intersection needs the evaluation time and match point of each expression are same.  The condition on syntactic equality of symbols must be relaxed and the conjunction of symbols must be considered by the algorithm. Worst case is mn  m = input number of left  n = input number of right   {s1[*]} && {s2;s3}

 Sequence fusion can be seen as an overlapped concatenation.  Worst case is m+n

A separate procedure is required to transform the sequence detection automation into a first-failure detection automaton. If the automata is NFA, it can’t be done. Classical determinization only consider symbol, but the symbol can be true simultaneously. This paper add boolean nature to this algorithm and form S- Determinize. The main idea of this algorithm is to catch the case where the automaton dies.

Take software metrics(Modelsim simulator) as a golden reference to ensure proper behavior of the assertion circuits. Using ISE i from Xilinx and XC2V FPGA to synthesize. The number of flip-flop and LUT and operating frequency are required to compare with FoCs. Assertion distance: the number of clock cycles in which the two assertion signals disagree.

N.A. happen when assertion circuit only contain FF or the FF has no feedback path. “r n” noted that Msim can’t catch failure, but MBAC can.

Assertion-based verification and emulation become increasingly important in verification, MBAC is a practical tool for generating assertion circuits. This paper show how to generate efficient circuits from sequence and introduced algorithms for implementing the sequence fusion and intersection operators. Experimental results show improvements in terms of the resource usage, behavior and capability of assertion circuits.

I think we can follow the same rule to generate circuit from SVA. Because SystemVerilog is more high level. We can rewrite protocol checker in SVA. SVA is more readable and more popular.