Talianpaip Talianpaip ialah satu teknik utk meningkatkan prestasi mesin dgn melakukan arahan bertindih utk mengurangkan masa perlaksanaan. Ini merupakan kunci kepantasan CPU pd hari ini. 1

Pipelining Is Natural! Laundry Example Aini, Boon, Chong, David each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 30 minutes “Folder” takes 30 minutes “Stasher” takes 30 minutes to put clothes into drawers ABCD

Sequential Laundry Sequential laundry takes 8 hours for 4 loads If they learned pipelining, how long would laundry take? 30 TaskOrderTaskOrder B C D A Time 30 6 PM AM

Pipelined Laundry: Start Work ASAP Pipelined laundry takes 3.5 hours for 4 loads! TaskOrderTaskOrder 12 2 AM 6 PM Time B C D A 30

Pipelining Lessons Talian tidak mempercepatkan pendaman satu tugas, ia mempercepatkan truput utk keseluruhan beban kerja. Multi tugas dilaksanakan serentak dgn menggunakan sumber yg berlainan. Keupayaan speedup = Bil. segmen talianpaip Kadar talianpaip dihadkan oleh segmen talianpaip yg terlembap Ketidakseimbangan pjg segmen talianpaip mengurangkan speedup Masa utk penuhkan talianpaip & pengosongan talianpaip mengurangkan speedup. 6 PM 789 Time B C D A 30 TaskOrderTaskOrder

Pengenalan Dlm sistem tipikal kepantasan dicapai melalui teknik keselarian dlm semua peringkat: Multi- user, multi-tasking, multi-processing, multi- programming, multi-threading, compiler optimizations. Talianpaip : adl teknik pertindihan operasi semasa perlaksanaan. Different types of pipeline: instruction pipeline, operation pipeline, multi-issue pipelines.

Apakah talianpaip? 2 Ia spt automobile assembly line. Ia m’punyai bbrp langkah atau langkah atau segmen. Setiap segmen melakukan arahan atau operasi yg berbeza. Segmen2 ini disambung menjadikan paip. An inst or operation enters through one end and progresses through the stages and exit through the other end. Talianpaip ialah teknik perlaksanaan yg mengeksplotasikan keselarian sesama arahan dlm aliran arahan berjujukan.

Krateria2 Talianpaip Truput: Bil. item (cars, instructions, operations) yg keluar drpd talianpaip per unit masa. –Ex: 1 inst / clock cycle, 10 cars/ hour, 10 fp operations /cycle. Masa segmen: Matlamat pereka talianpaip ialah keseimbangan masa setiap segmen talianpaip. (Balanced pipeline) –masa segmen = Masa arahan dlm mesin yg bukan talianpaip / bil.segmen. –Dlm kebanyakan kes, masa segmen = mak (masa utk semua segmen). CPI : Pipeline yields a reduction in cycles per instruction. CPI approx = stage time.

A Machine Without Pipelines I1I2I3 Below is a diagram which shows the execution of three instructions in sequence. Computer Instructions Execution Time

A Machine With Pipelines I1 I2 I3 Computer Instructions } Instructions are overlapped Time Below is a diagram to show the execution of three instructions which are overlapped. Execution Time

Instruction Composition A single instruction executing within a machine normally consist of a few segments which performs specific tasks. An example of an instruction which has 6 segments:- 1)Fetch instruction from memory. (IFetch) 2)Decode the instruction. (Dcd) 3)Calculate the effective address. (Eadd) 4)Fetch operand from memory. (Mem) 5)Execute the instruction. (Exec) 6)Store results in the proper place (or location). (WB)

Space Time Diagram A space-time diagram is normally used to represent the execution of instructions in a pipeline. Below is an example of a space time diagram. Whereby there are six instructions executing (I1 to I6) and each instruction has four segments. IFetchDcdExecMemWB IFetchDcdExecMemWB IFetchDcdExecMemWB IFetchDcdExecMemWB IFetchDcdExecMemWB IFetchDcdExecMemWB Program Flow Time

Pipeline Performance - Example2 Assume times for five functional units of a pipeline to be: 10ns, 8ns, 10ns, 10ns and 7ns. Overhead 1ns per stage. Compute the speed of the data path. Pipelined: Stage time = MAX(10,8,10,10,10,7) + overhead = = 11ns. This is the average instruction execution time at steady state. Non-pipelined: = 45ns Speedup = 45/11= 4.1 times

Masalah2 Talianpaip Kebergantungan Data Masalah yg wujud pabila dua arahan bersebelahan dalam talian paip ingin mencapai secebis data yg berada dlm lokasi memori yg sama. Percabangan Arahan Masalah yg berlaku pabila branch perlu dilaksanakan dan arahan2 pre-fetched yg lain dlm talian paip akan/mesti dibuang.

Kebergantungan Data Dlm cth ini, andaikan arahan terdiri drpd 4 segment, dan arahan satu (I1) dan arahan dua (I2) mencapai lokasi memori yg sama. FIDAFOEXFIDAFOEX Instruction Execution I1 I2 Both instructions are trying to access the same variable at the same time.

Selesaian Masalah Kebergantungan Data Hardware Interlocks (membabitkan perkakasan) Operand Forwarding (membabitkan perkakasan) Delayed Load (membabitkan perisian)

Hardware Interlocks FIDAFOEX FIDAFOEX Instruction Execution I1 I2 Ia mengesan masalah kebergantungan data dan lengahkan arahan kedua.

Operand Forwarding Ia mengesan masalah kebergantungan data dan hantar (forwards) keputusan arahan satu ke dlm arahan berikutnya. FIDAFOEXFIDAFOEX Instruction Execution I1 I2 The offending instructions will have the output of one, sent directly into the next instruction.

Delayed Load Ia mengesan masalah kebergantungan data ketika aturcara tersebut dikompilasikan. Pengkompilasi kemudiannya akan memasukkan arahan no-operation di antara arahan2 yg terbabit. FIDAFOEX FIDAFOEX Instruction Execution I1 I2 FIDAFOEX NOP

Percabangan Arahan What if instruction I1 is a branch instruction to I3? what happens to I2? FIDAFOEXFIDAFOEX Instruction Execution I1 I2 FIDAFOEX I3

Selesaian Arahan Bercabang Pre-fetch Target Instruction Branch Target Buffer, A form of cache implementation (but for instructions) Loop Buffer Find out more details for these Branch Prediction solutions.. Delayed Branch

Operasi Talianpaip Apakah yg memudahkan? –Semua arahan adl sama panjang –sedikit format arahan –memori operan hanya wujud ketika muat & simpan Apakah yg menyusahkan? –Katakan hanya ada satu memori (structural hazard) –masalah arahan2 bercabang (control hazard) –Arahan yg bergantung kpd arahan sebelumnya (data hazards)

Bencana Talianpaip Bencana akan mengurangkan prestasi talian drpd ideal speedupnya: Structural hazard: Konflik sumber. Perkakasan tidak boleh menyokong kesemua arahan gabungan yg wujud dlm simultaneous overlapped execution. Data hazard: Pabila arahan memerlukan keputusan drpd arahan sebelumnya. Control hazard: Akibat drpd cabangan2 & arahan lain yg memberi kesan kpd PC.

Structural Hazards Pabila lebih drpd satu arahan dlm talianpaip yg ingin mencapai sumber di mana ini menyebabkan laluan data mengalami structural hazard. Cth sumber spt: register file, memori, ALU. Selesaian: Melengahkan talianpaip utk satu kitaran jam apabila konflik tersebut dikesan. Hasilnya ialah pipeline bubble. Komflik capaian memori dan bgmn ia diatasi dengan melengahkan arahan. Problem: one memory port.

Data Hazard Consider the inst sequence: ADD R1,R2,R3 ; result is in R1 SUB R4,R5,R1 AND R6,R1,R7 OR R8,R1,R9 XOR R10,R1,R11 All instructions use R1 after the first inst.

Selesaian- Data Hazard Selalunya diselesaikan oleh data forwarding atau register forwarding (bypassing or short-circuiting). Bgmn? The data selected is not really used in identification flag (ID) but in the next stage: ALU. Forwarding works as follows: Keputusan ALU drpd buffer EX/MEM selalunya disuapbalik ke selak input ALU. If the forwarding hardware detects that its source operand has a new value, the logic selects the newer result than the value read from the register file.

Perlengahan Talianpaip Stall adl perlengahan dlm kitaran yg disbbkan oleh sebarang bencana yg tlh dinyatakan. Speedup : 1/(1+pipeline stall per instruction)* Number of stages Jadi apakah speedup utk talianpaip unggul tanpa stall? Bil. Kitaran yg diperlukan utk pemenuhan talian paip mungkin boleh dimasukkan dlm penghitungan kepurataan stall per arahan.