POWERPC ELEC 5200/6200 Computer Architecture and Design, Fall 2006 Lectured by Dr. V. Agrawal Lectured by Dr. V. Agrawal HARISH KONGARA.

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Presentation transcript:

POWERPC ELEC 5200/6200 Computer Architecture and Design, Fall 2006 Lectured by Dr. V. Agrawal Lectured by Dr. V. Agrawal HARISH KONGARA

What do the world’s fastest supercomputer, network and communications equipment such as Internet routers and switches, the Mars Rover, consumer electronics such as set top boxes, and the game consoles all have in common? They are powered by microprocessors based on IBM’s Power Architecture instruction set. POWER is a RISC instruction set architecture designed by IBM. The name is a backronym for Performance Optimization With Enhanced RISC

RISC VS CISC CISC MUL 2:3,5:2 RISC LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A

POWER ARCHITECTURE The First RISC Chip Design was 801 cpu. The Power Architecture Design is a descended directly from the 801 cpu. The power architecture design was interested primarily in fixing 2 problems of 801 cpu design  the 801 required all instructions to complete in one clock cycle, which eliminated floating point instructions  although the decoder was pipelined as a side effect of these single-cycle operations, they didn't use superscalar effects

POWERPC PowerPC is largely based on IBM's POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation.

The PowerPC architecture is a modified version of the POWER architecture. The PowerPC architecture added  single-precision floating point instructions  general register-to-register multiply and divide instructions, and  removed some POWER features such as the specialized multiply and divide instructions using the MQ register. It also added a 64-bit version of the architecture. POWERPC AND POWER ARCHITECTURE

POWERPC FAMILY OF MICROPROCESSORS The 601 is a fusion of the POWER architecture and the PowerPC architecture. It is designed to drive mainstream desktop systems. A Macintosh with a 601 will deliver integer performance three to five times that of today’s high-end based Macintosh systems and floating point performance around ten times that of today’s high-end based Macintosh systems The 603 is the first PowerPC only implementation of the PowerPC architecture. It is designed for low-cost and low-power consumption. The 603 will be used in portable and low-cost desktop Macintosh with PowerPC systems. In many ways, over time the 603 could become Apple’s replacement for the The 604 is designed for mainstream desktop personal computers. It will cost about as much as the 601, but will deliver higher performance The 620, which is currently still in the design phase, is a high- performance microprocessor that Motorola and IBM believes will be well-suited for very high-end personal computers, workstations, servers, and multiprocessor systems.

POWERPC VS PENTIUM How the 601 stacks up against Intel’s state-of-the-art CISC design, the “Pentium.” On a basis of price, performance, and power consumption, the PowerPC 601 compares quite favorably. The 601 delivers integer performance that matches and floating-point performance that exceeds Pentium’s for about half the cost. In addition it consumes about half the power of Pentium. Pentium PowerPC 601 Frequency 66 MHz 66 MHz Die Size 264 mm2 120 mm2 Cache 16K 32K Power 14 Watts 9 Watts SPECInt SPECfp Price $ $450.00

APPLE LIKE RISC The above comparison give us an idea why Apple is staking such a large part of its future on RISC. The PowerPC 601 is the first of its generation matches the performance of the latest CISC chips - and the next PowerPC implementation (603) is well under way. While CISC designers have to work increasingly hard to squeeze more performance out of their designs, at an ever increasing manufacturing cost, RISC designs have considerable room for growth. The evolution of RISC designs has the potential to outstrip the evolution of CISC.

QUICK TOUR OF 601

OPTIMIZING CODE FOR POWERPC INSTRUCTION SCHEDULING LOADING REGISTERS SCRATCH REGISTERS

REFERENCES

THANKS