F.F. Dragan (Kent State) A.B. Kahng (UCSD) I. Mandoiu (UCLA/UCSD) S. Muddu (Sanera Systems) A. Zelikovsky (Georgia State) Practical Approximation Algorithms for Separable Packing LPs

2 Outline VLSI design motivation –Global routing via buffer-blocks –Separable packing ILP formulations PTAS for separable packing LPs Analysis Experimental results

3 Outline VLSI design motivation –Global routing via buffer-blocks –Separable packing ILP formulations PTAS for separable packing LPs Analysis Experimental results

4 Outline VLSI design motivation –Global routing via buffer-blocks –Separable packing ILP formulations PTAS for separable packing LPs Analysis Experimental results

5 Outline VLSI design motivation –Global routing via buffer-blocks –Separable packing ILP formulations PTAS for separable packing LPs Analysis Experimental results

6 VLSI Global Routing

7 Buffered Buffer Blocks

8 Problem Formulation Global Routing via Buffer-Blocks (GRBB) Problem Given: BB locations and capacities List of multi-pin nets – upper-bound on #buffers for each source-sink path L/U bounds on the wirelength b/w consecutive buffers/pins Find: Buffered routing of a maximum number of nets subject to the given constraints

9 Integer Program Formulation

10 Enforcing Parity Constraints Inverting buffers change the polarity of the signal Each sink has a given polarity requirement  Parity constraints for the #buffers on each routed source-sink path  A path may use two buffers in the same buffer block Integer program changes Split each BB vertex r of G into two copies, r’ and r’’ Impose capacity constraint on the sets of vertices {r’,r’’}

11 Combining with compaction

12 Combining with compaction

13 Combining with compaction Set capacity constraints: cap(BB1) + cap(BB2)  const.

14 GRBB with Buffer Library Discrete buffer library: different buffer sizes/driving strengths  Need to allocate BB capacity between different buffer types Integer program changes Replace each BB vertex r of G by a set X(r) of vertices (one for each buffer type) Modify edge set of G to take into account non-uniform driving strengths Impose capacity constraint on the sets of vertices X(r):

15 “Relax+Round” Approach to GRBB 1.Solve the fractional relaxation –Exact linear programming algorithms are impractical for large instances –KEY IDEA: use an approximation algorithm allows fine-tuning the tradeoff between runtime and solution quality 2.Round to integer solution –Provably good rounding [RT87] –Practical runtime (random-walk based)

16 Outline VLSI design motivation –Global routing via buffer-blocks –Separable packing LP formulations PTAS for separable packing LPs Analysis Experimental results

17 Separable Packing LP

18 Previous Work MCF and packing/covering LP approximation: [FGK73,SM90, PST91,G92,GK94,KPST94,LMPSTT95,R95,Y95,GK98,F00,…] Exponential length function to model flow congestion [SM90] Shortest-path augmentation + final scaling [Y95] Modified routing increment [GK98] Fewer shortest-path augmentations [F00] We extend speed-up idea of [F00] to separable packing LPs

19 Separable Packing LP Algorithm w(X)  , f  0,  =  For i = 1 to N do For k = 1, …, #nets do Find min weight feasible Steiner tree T for net k While weight(T) < min{ 1, (1+  )  } do f(T)= f(T) + 1 For every X do w(X)  ( 1 +   (T,X)/cap(X) ) * w(X) End For Find min weight feasible Steiner tree T for net k End While End For  = (1+  )  End For Output f/N

20 Outline VLSI design motivation –Global routing via buffer-blocks –Separable packing ILP formulations PTAS for separable packing LPs Analysis Experimental results

21 Runtime Dual LP: Choose #iterations N such that all feasible trees have weight  1 after N iterations (i.e.,   1) Tree weight lower bound is  initially, and is multiplied by ( 1+  ) in each iteration

22 Approximation Guarantee Theorem: For every  <.15, the algorithm finds factor 1/(1+4  ) approximation by choosing where L is the maximum number of vertices in a feasible Steiner tree. For this value of , the running time is

23 Outline VLSI design motivation –Global routing via buffer-blocks –Separable packing ILP formulations PTAS for separable packing LPs Analysis Experimental results

24 Implementation choices 2-Pin3,4-pinMulti-pin DecompositionStar, Minimum Spanning tree Matching, 3-restricted Steiner tree Not needed Min-weight DRSTShortest path (exact) Try all Steiner pts + shortest paths (exact) Very hard!  heuristics RoundingRandom-walkBackward random-walks

25 1.Store fractional flows f(T) for every feasible Steiner tree T 2.Scale down each f(T) by 1-  for small  3.Each net k routed with prob. f(k)=  { f(T) | T feasible for k }  Number of routed nets  (1-  )OPT 4.To route net k, choose tree T with probability = f(T) / f(k)  With high probability, no BB capacity is exceeded Problem: Impractical to store all non-zero flow trees Provably Good Rounding

26 1.Store fractional flows f(T) for every valid routing tree T 2.Scale down each f(T) by 1-  for small  3.Each net k routed with prob. f(k)=  { f(T) | T routing for k }  Number of routed nets  (1-  )OPT 4.To route net k, choose tree T with probability = f(T) / f(k)  With high probability, no BB capacity is exceeded Random-Walk 2-TMCF Rounding use random walk from source to sink Practical: random walk requires storing only flows on edges

27 Random-Walk MTMCF Rounding S T1 T2 T3 Source  Sinks

28 Random-Walk MTMCF Rounding S T1 T2 T3 Source  Sinks

29 The MTMCF Rounding Heuristic 1.Round each net k with probability f(k), using backward random walks –No scaling-down, approximate MTMCF < OPT 2.Resolve capacity violations by greedily deleting routed paths –Few violations 3.Greedily route remaining nets using unused BB capacity –Further routing still possible

30 Implemented Heuristics Greedy buffered routing: 1.For each net, route sinks sequentially along shortest paths to source or node already connected to source 2.After routing a net, remove fully used BBs Generalized MCF approximation + randomized rounding –G2TMCF –G3TMCF (3-pin decomposition) –G4TMCF (4-pin decomposition) –GMTMCF (no decomposition, approximate DRST)

31 Experimental Setup Test instances extracted from next-generation SGI microprocessor Up to 5,000 nets, ~6,000 sinks U=4,000  m, L=500-2,000  m 50 buffer blocks buffers / BB

32 % Routed Nets vs. Runtime

33 Conclusions and Ongoing Work Provably good algorithms and practical heuristics based on separable packing LP approximation –Higher completion rates than previous algorithms Extensions: –Combine global buffering with BB planning –Buffer “site” methodology  tile graph –Routing congestion (channel capacity constraints) –Simultaneous pin assignment

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35 % Sinks Connected #sinks/ #nets Greed G2TMCFG3TMCFG4TMCFGMTMCF  =.64  =.04  =.64  =.04  =.64  =.04  =.64  = / / / / / /

36 Runtime (sec.) #sinks/ #nets Greed G2TMCFG3TMCFG4TMCFGMTMCF  =.64  =.04  =.64  =.04  =.64  =.04  =.64  = / , , / , , / , , / , , , / , , , / , , ,833

37 Resource Usage Greed G2TMCFG3TMCFG4TMCFGMTMCF  =.64  =.04  =.64  =.04  =.64  =.04  =.64  =.04 # Conn. Sinks 5,6455,7255,8425,7795,8965,8275,9425,8135,897 % Conn. Sinks WL (meters) WL/sink (microns) 7,4797,8918,1827,6978,0837,5827,9927,7988,057 #Buff90379,86010,6769,59110,6109,49710,5079,86010,647 #Buff/sink #nets = 4,764 #sinks = 6, buffers/BB

38 Resource Usage for 100% Completion Greed  =.04 4TMCF,  =.04 #buffers/BB1,000 or INF ,000INF WL (meters) WL/sink (microns) 7,9318,1918,2128,2788,513 #Buff10,33011,07911,11511, #Buff/sink #nets = 4,764 #sinks = 6,038MTMCF wastes routing resources!