:: Discrete Cosine Transformation

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Presentation transcript:

:: Discrete Cosine Transformation Tommy Taylor Brandon Hsiung Changshi Xiao Bongkwan Kim Paradigm

::welcome Discrete Cosine Transformation Boring math leads to great applications: MPEG2, DVD, HDTV, MP3 Paradigm

::Application An image codec example (JPEG) : DCT Quant. Huffman encoding Storage/ transmission channel IDCT deQuant. Huffman decoding Paradigm

::2D DCT Definition Xm,n=(C(m)C(n)/4)*i=0,7 j=0,7xi,jcos((2i+1)m/16)cos((2j+1)n /16) Where C(m),C(n) are constants: C(n) = 1/sqrt(2) , if n = 0 or 1 , if n  0 It can be decomposed into two 1D DCT, first apply on rows , then on columns. 1D DCT is defined as : Xn = (C(n)/4)*i=0,7 xicos((2i+1)n/16) Paradigm

::Fast Algorithm of 1D DCT A A A A A C -A -B A -C -A B A -B B -C D E F G E -G -D -F F -D -G E G -F E -D x0 + x7 x1 + x6 x2 + x5 x3 + x4 X0 X2 X4 X6 x0 - x7 x1 - x6 x2 - x5 x3 - x4 X1 X3 X5 X7 = A = cos(/4) B = cos(/8) C = sin(/8) D = cos(/16) E = cos(3/16) F = sin(3/16) G = sin(/16) Paradigm

This is what we’re going to do ! ::2D DCT Architecture Data in This is what we’re going to do ! 1D DCT (on rows) Transpose RAM 1D DCT (on columns) Data out Paradigm

+ -  1D DCT : direct implementation, none real time processing R0 Selector R1 R2 R3 R4 R5 R6 R7 + - R8 R9  R10 R12 R13 Parallel to serial Control logic ROM R11 in_data(16) in_valid out_valid out_ready out_done clk vdd vss reset out_data(16) Paradigm

-  + 1D DCT : parallel architecture for real time processing R0 R1 R2 Selector R16 + R20 Parallel to serial Control logic ROM R17 - R8 R9 R10 R11 R12 R13 R14 R15  R22 R18 R21 R19 R23 in_data(16) clk vdd vss out_done out_data(16) in_run Paradigm

::Transistor Estimate architecture Adder Multiplier register ROM control total pins A1 4x16x30 2 x 4000 14x16x20 7x16 1000 15512 40 A2 12x16x30 4 x 4000 24x16x20 14x16 30664 37 architecture latency throughput Real time Clock A1 14 cycle 2samples /6 cycle No ? A2 12 cycle 1 sample/cycle Yes Paradigm

::Design Goals High throughput, real time, 1sample/clock Clock rate, 70 - 100 MHz (for HDTV applications) Area, ~30k, can we afford it ??? Paradigm

:: Secondary Ideas Motion Prediction for DVD-Video Serpent Encryption Paradigm

::conclusion & questions Paradigm