© 2006 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPresentation_ID 1 Resolving Power to Ground Shorts in a Low Resistance Environment Steve.

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Presentation transcript:

© 2006 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPresentation_ID 1 Resolving Power to Ground Shorts in a Low Resistance Environment Steve Butkovich Steve Lee

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 2 What is the problem?  Large Number of Devices Failing at ICT  Most of the shorts failures were attributed to component problems  RMA of components to the vendors found no defect Failures (PPM)

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 3 The Small Geometry Devices Have High Leakage  As Semiconductor Device Geometries Decrease Leakage Current is Increasing 90 and 65 nm are common 45 nm becoming available, 32 nm is on the near term roadmap  Core Resistance is Low and Variable Frequently the Resistance Range is Unpublished

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 4 90 nm ASIC – 1.5 volt Core to GND at 200 mv samples

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 5 How do we differentiate a solder short?  The ICT System Shorts Test won’t work!  Four Wire / Four Probe Measurement  Power Up Test  Re-Verification Test

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 6 Four Wire / Four Probe  Resistance Variation Across the Probe/Test Point Contact has too much variation  Power and Ground Nets typically have multiple test points Drive +Sense +Sense -Drive -

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 7 Power Up Test  Limited Current Power Up  Most of the Semiconductor Cores Draw About 2 to 10 Watts in Quiescent ICT State  Measurement of Voltage will show whether devices successfully power

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 8 Re-Verification Test  Verify whether a short exists before doing unnecessary rework DMM verification

© 2006 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPresentation_ID 9 Tantalum Capacitor “Proofing” Steve Butkovich

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 10 The Problem  High Failure Rate of Tantalum Capacitors Manufactured by Kemet Possibly Other Manufacturers  This is NOT my paper or research  Sharing application and industry data that may concern test

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 11 Problem Cause  CTE Mismatch during reflow/cooling causing dielectric faults  Proofing migrates problems that are caused in reflow in the Mn0 2 dielectric

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 12 Proofing Procedure (or controlled Power Up)  Application of the Selected Voltage through a 1000 ohm resistor  After 7 seconds, verify that the voltage is within 99% of rated voltage If not, repeat  Proofing Voltage is based on Capacitor Working Voltage Can be up to Working Voltage + 4 volts  May Not be Practical Due to Other Devices on Board

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 13 Results of Proofing

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 14 Board Test as a Proofing Location  Structural Test Team is getting requests to implement proofing  Test Time factors may make ICT an undesirable location for proofing

© 2008 Cisco Systems, Inc. All rights reserved.Cisco PublicASIC Power / GND 15