On-the-fly Synthesis of Multi-Clock SVA Jiang Long Andrew Seawright Paparao Kavalipati IWLS’ 2008

2 Outline n Introduction — Background and scope — Related works n Synthesizing multi-clock SVA — Single clock assertion compilation — Compile through rewriting — On-the-fly synthesis algorithm n Proof of correctness n Experimental results and conclusions

3 Formal Model for Multi-Clock Designs Clock Specification RTL Design SVA Assertions

4 Multi-Clock Modeling mclk

5 Objective n Synthesize SVA into Checker logic — Generic checker logic n Utilize existing FV framework/technique/optimization n Utilize existing multi-clock network — Optimize checker logic size n Number of sequentials and gates — Validation n Proof of correctness

6 SVA Abstract Grammar – Unclocked Sequence Sequences define language of words n Booleans b n Concatenation R 1 ##1 R 2 n Or R 1 or R 2 n Repetition R 1 [*0:$] n Fusion R 1 ##0 R 2 n Intersect R 1 intersect R 2 n Local Variable b, v=e

7 SVA Abstract Grammar – Clocked Sequence n Grammar for clocked sequence S S R | ( S ##1 S) n Single R n 1 R 1 2 R 2

8 SVA Abstract Grammar - Property Properties evaluate true/false over words n Regular expression R n Implication R |-> P R |=> P n Or P 1 or P 2 n And P 1 and P 1 n Not not P

9 SVA Abstract Grammar - Property Properties evaluate true/false over finite words n Implication R |-> P R |=> P

10 SVA Multi-Clock Assertions

11 SVA Multi-Clock Assertions

12 SVA Multi-Clock Assertions

13 SVA Multi-Clock Assertions

14 SVA Multi-Clock Assertions

15 n Synthesis of regular expression + “actions” — Seawright / Brewer - synthesis of controllers n Synthesis of SVA — Pellauer / Lis / Baltus / Nikhil - using Blue Spec n Checkers in Formal Verification — Beer / Ben-David / Landver: on-fly-model checking of RCTL n Synthesis of SVA Local Variables — Long/Seawright n Multi-Clock assertion synthesis for verification — Ganai, et al. n Annotating OVL 2.0 with SVA — Long, Seawright, et al. Related Work

16 Contribution n Synthesize SVA into Checker logic — Adapt single-clock SVA compilation procedure — Generic checker logic n Utilize existing FV framework/technique/optimization n Utilize existing multi-clock network — Optimized checker logic size — Validation n Proof of correctness based on SVA semantics

17 Outline n Introduction — Background and scope — Related works n Synthesizing Multi-clock SVA — Single clock assertion compilation — Compile through semantic rewriting n Penalty: Double the checker logic size — On-the-fly synthesis algorithm n No penalty n Proof of correctness n Experimental results and conclusions

18 SVA compilation Prop Bool R |=> term [*2:M] gnt req1 ##1 req0 term Property clk0) req0 ##1 req1[*2:M] |=> gnt; endproperty

19 SVA Compilation Sketch 1. Construct sequence recognizer machines for LHS and RHS sequences (this step is most relevant to this work) 2. From analysis and transformation of these LHS and RHS sequence recognizer machines, construct the failure circuit for the overall implication property (not the focus of this work)

20 |=> term [*2:M] gnt req1 ##1 req0 term Recursive Construction

21 |=> term [*2:M] gnt req1 ##1 req0 term Recursive Construction

22 R1 ##1 R2 R1 APAP start R2 APAP start clk start APAP R1R1 R2R2 ##1

23 R1 ##0 R2 R1 APAP start R2 APAP start APAP

24 R1 ##0 R2 R1 APAP start R2 APAP start APAP R is equivalent to (R ##0 1) (1 ##0 R)

25 Outline n Introduction — Background and scope — Related works n Synthesizing Multi-clock SVA — Single clock assertion compilation — Compile through semantic rewriting n Penalty: Double the checker logic size — On-the-fly synthesis algorithm n No penalty n Proof of correctness n Experimental results and conclusions

26 SVA Semantic Rewriting Rules

27 Rewriting: An Example

28 Synthesize Through Rewriting |=> ##1 req0 term req1 term gnt term [*2:3]

29 Synthesiz3 Through Rewriting |=> ##1 req0 term req1 term gnt term [*2:3] 1. Checker logic: Correct by Construction

30 Synthesis Through Rewriting |=> ##1 req0 term req1 term gnt term [*2:3] 2. Rewriting rule (2.1): size of the tree doubled 1. Checker logic: Correct by Construction

31 On-the-fly Synthesis n Motivation — Avoid the penalty from the rewriting — Model clock directly n Compilation procedure — Annotate syntax tree with clock information — Adapt to existing recursive compilation — Model clocked constructs directly — Proof of correctness through construction

32 Annotated Abstract Syntax Tree Prop Bool R |=> term [*2:M] gnt req1 ##1 req0 term clk 2 clk 1 clk 2 clk 3 clk 2

33 Annotated Abstract Syntax Tree Prop Bool R |=> term [*2:M] gnt req1 ##1 req0 term clk 2 clk 1 clk 2 clk 3 clk 2

34 Annotated Abstract Syntax Tree Prop Bool R |=> term [*2:M] gnt req1 ##1 req0 term clk 2 clk 1 clk 2 clk 3 clk 2

35 On-the-fly Model n Annotated node with a single clock (b) (R 1 ##1 R 2 ) n Annotated node with two different clocks 1 R 1 R 2

36 Basic Block

37 Basic Block 1 ##1 R 2 )

38 Basic Block 1 ##1 R 2 )

39 Building Block 1 R 1 2 R 2

40 Building Block 1 R 1 2 R 2

41 Building Block 1 R 1 2 R 2 s0 <= ( R 1.A p 1 ) || ( s0 && 2 )

42 NFA 1 R 1 2 R 2

43 Outline n Introduction — Background and scope — Related works n Synthesizing Multi-clock SVA — Single clock assertion compilation — Compile through semantic rewriting n Penalty: Double the checker logic size — On-the-fly synthesis algorithm n No penalty n Proof of correctness n Experimental results and conclusions

44 SVA Rewriting Rules

45 Proof of Correctness n Lemmas 1. R equals. R ## R equals. 1 ##0 R

46 Proof of Correctness n Lemmas 1. R equals. R ## R equals. 1 ##0 R R ( R ##0 1 ) R ( 1 ##0 R)

47 n Lemmas 1. R equals. R ## R equals. 1 ##0 R R ( R ##0 1 ) R ( 1 ##0 R) R 1 R R R 1 Proof of Correctness

48 Proof of Correctness n Lemmas 1. R equals. R ## R equals. 1 ##0 R R ( R ##0 1 ) R ( 1 ##0 R) R 1 R R R 1 1 R 1 2 R 2

49 Proof of Correctness n Lemmas 1. R equals. R ## R equals. 1 ##0 R R ( R ##0 1 ) R ( 1 ##0 R) R 1 R R R 1 1 R 1 2 R 2 1 (R 1 ##0 1) 2 ( 1 ##0 R 2 )

50 Proof of Correctness n Lemmas 1. R equals. R ## R equals. 1 ##0 R R ( R ##0 1 ) R ( 1 ##0 R) R 1 R R R 1 1 R 1 2 R 2 1 (R 1 ##0 1) 2 ( 1 ##0 R 2 ) 1 R R 2

51 Proof 1 R R 2

52 Proof 1 R R 2

53 Proof 1 R R 2

54 Proof 1 R R 2 9. !clk 1 [*0:$] ##1 clk 1 ##1 !clk 2 [*0:$] ##1 clk 2

55 Proof !clk 1 [*0:$] ##1 clk 1 ##1 !clk 2 [*0:$] ##1 clk 2 1 R R 2 9. !clk 1 [*0:$] ##1 clk 1 ##1 !clk 2 [*0:$] ##1 clk 2

56 Proof !clk 1 [*0:$] ##1 clk 1 ##1 !clk 2 [*0:$] ##1 clk 2 1 R R 2 9. !clk 1 [*0:$] ##1 clk 1 ##1 !clk 2 [*0:$] ##1 clk 2

57 Proof !clk 1 [*0:$] ##1 clk 1 ##1 !clk 2 [*0:$] ##1 clk 2 1 R R 2 9. !clk 1 [*0:$] ##1 clk 1 ##1 !clk 2 [*0:$] ##1 clk 2

58 Special 1 ##1 R 2 )

59 clk 1 ==clk 2 Special 1 ##1 R 2 )

60 Experimental Results

61 Experimental Results

62 Experimental Results 2x

63 Conclusion n Efficient synthesis of multi-clock assertions — Create a generic checker logic — Direct modeling to avoid the doubling penalty — Proof of correctness

On-the-fly Synthesis of Multi-Clock SVA Jiang Long Andrew Seawright Paparao Kavalipati IWLS’ 2008