3. Digital Implementation of Mo/Demodulators

General Structure of a Mo/Demodulator amp DSB SSB DEM

Single Side Band (SSB) Modulator

Implementation using Real Components SSB where

Single Side Band (SSB) Demodulator LPF

Single Side Band (SSB) Modulator in Discrete Time Modulator Implemented in two stages: Digital Up Converter DUC Analog MOD ZOH DISCRETE TIME CONTINUOUS TIME

Single Side Band (SSB) Demodulator in Discrete Time Demodulator Implemented in two stages: Digital Down Converter DDC Analog DEM ZOH CONTINUOUS TIME DISCRETE TIME

Digital Down (DDC) and UP (DUC) Converters RF Baseband MHz for voice GHz for data kHz for voice MHz for data Order of magnitude of resampling:

Problem with Large Upsampling Factor LPF if M is large, very small transition region high complexity filter

Problem with Large Downsampling Factor LPF LPF if M is large, very small transition region high complexity filter

Solution: Upsample in Stages In order to make it more efficient we upsample in L stages

i-th Stage of Upsampling

Example: Upsample in One Stage This is not only a filter with high complexity, but also it is computed at a high sampling rate.

Same Example in Three Stages Total Number of operations/sec= a 95% savings!!!!

Downsample in Stages

i-th Stage of Downsampling noise keep aliased noise away from signal

Example: Downsample in One Stage

Same Example in Three Stages Total Number of operations/sec = … a savings of almost 99% !!!

Stages at the Highest Rates the highest sampling rates are close to carrier frequencies, thus very high; properly choose intermediate frequencies to have simple filters at highest rates

Last Stage in UpSampling wide region

First Stage in DownSampling wide region

Very simple Low Pass Filter: the Comb Integrator Cascade (CIC) same!!! “Comb” “Integrator” these two are the same! Notice: no multiplications!

Frequency Response of the Comb Filter …like a comb!

Impulse Response of the CIC interpolating sequence

The CIC in the Time Domain like a discrete time ZOH!

Two Important Identities: The “Noble” Identities Same !!! As a consequence we have one of two “Noble Identities”: Same!!!

Other “Noble” Identity Same !!! As a consequence we have the other of the two “Noble Identities”:

Efficient Implementation of Upsampling CIC Use Noble Identity: Very simple implementation (no multiplications):

Efficient Implementation of Downsampling CIC Use Noble Identity: Very simple implementation (no multiplications):

Frequency Response of the CIC 0.1 0.2 0.3 0.4 0.5 -25 -20 -15 -10 -5 5 f=F/Fs dB only 13 dB attenuation Not a very good Low Pass Filter. We want a better attenuation in the stopband!

Put M Stages together Frequency Response:

Improved Frequency Response of CIC Filter Resampling Factor N=10 With M=4 or 5 we already get a very good attenuation.

Example: M=4 Stages

Implementation of M Stage CIC Filter: Upsampling Use Noble Identity:

Implementation of M Stage CIC Filter: Downsampling Use Noble Identity:

Problem: DownSampling CIC is Unstable Now we have to be careful: the output of the integrator will easily go to infinity

CIC Implementation. At the p stage: This implies: and

If we use Q bits for the integrators then we need to guarantee Let the input data use L bits: Then: decimation factor input bits number of stages

Application: Software Defined Radio Definitions: Software Defined Radio: modulation, bandwidth allocation … all in software Field Programmable Gate Array (FPGA): reprogrammable logic device which is able to perform a number of operations in parallel. They can process data at a rate of several 100s of MHz DSP Chip: optimized for DSP operations by some hardwired ops (such as multiplies).

An HF SSB Software Defined Radio by Dick Benson, The Mathworks, 64MHz 15.6kHz 7.8kHz RF IQ AUDIO Rec. Rec. Rec/Tr Trans. Trans. DAC IQ AUDIO RF FPGA DSP Chip

Transmitter: I SSB Q DSP Chip I RF Q FPGA AUDIO FIR FIR Xilinx Library Modules I FIR FIR CIC RF Q FIR FIR CIC FPGA

Receiver: I RF Q FPGA I Q DSP Chip Xilinx Library Modules CIC FIR FIR AUDIO Q FIR DSP Chip