Based on slides by: Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 8 – Systematic Simplification.

Slides:



Advertisements
Similar presentations
CS 121 Digital Logic Design
Advertisements

KU College of Engineering Elec 204: Digital Systems Design
Overview Part 1 – Gate Circuits and Boolean Equations
K-Map Simplification COE 202 Digital Logic Design Dr. Aiman El-Maleh
ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 6 Dr. Shi Dept. of Electrical and Computer Engineering.
Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Chapter 2 – Combinational.
CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.
Give qualifications of instructors: DAP
Computer Engineering (Logic Circuits) (Karnaugh Map)
ECE 331 – Digital System Design Karnaugh Maps and Determining a Minimal Cover (Lecture #7) The slides included herein were taken from the materials accompanying.
SYEN 3330 Digital Systems Jung H. Kim Chapter SYEN 3330 Digital Systems Chapter 2 – Part 5.
CSCE 211: Digital Logic Design
EECC341 - Shaaban #1 Lec # 7 Winter Combinational Circuit Minimization Canonical sum and product logic expressions do not provide a circuit.
IKI a-Simplification of Boolean Functions Bobby Nazief Semester-I The materials on these slides are adopted from those in CS231’s Lecture.
Overview Part 2 – Circuit Optimization 2-4 Two-Level Optimization
CT455: Computer Organization K-Map
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Chapter 2 – Combinational.
1 Chapter 5 Karnaugh Maps Mei Yang ECG Logic Design 1.
Department of Computer Engineering
CHAPTER 1 INTRODUCTION TO DIGITAL LOGIC. K-Map (1)  Karnaugh Mapping is used to minimize the number of logic gates that are required in a digital circuit.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 2 – Combinational Logic Circuits Part 2.
Optimization Algorithm
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. Circuit Optimization Logic and Computer Design Fundamentals.
ECE 3110: Introduction to Digital Systems Symplifying Products of sums using Karnaugh Maps.
Combinational Logic Part 2: Karnaugh maps (quick).
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 2 – Combinational Logic Circuits Part 2.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 2 – Combinational Logic Circuits Part 2.
Gate-level Minimization
Computer Engineering (Logic Circuits) (Karnaugh Map)
Chapter3: Gate-Level Minimization Part 1 Origionally By Reham S. Al-Majed Imam Muhammad Bin Saud University.
Chapter 3 The Karnaugh Map
07 KM Page 1 ECEn/CS 224 Karnaugh Maps. 07 KM Page 2 ECEn/CS 224 What are Karnaugh Maps? A simpler way to handle most (but not all) jobs of manipulating.
CHAPTER 3: PRINCIPLES OF COMBINATIONAL LOGIC
Ahmad Almulhem, KFUPM 2010 COE 202: Digital Logic Design Combinational Logic Part 3 Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:
Prof. Hsien-Hsin Sean Lee
1 Example: Groupings on 3-Variable K-Maps BC F(A,B,C) = A ’ B ’ A BC F(A,B,C) = B ’ A
ECE/CS 352 Digital System Fundamentals1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapter 2 – Part 5 Tom Kaminski & Charles R. Kime.
Karnaugh Map (K-Map) By Dr. M. Khamis Mrs. Dua’a Al Sinari.
1 Gate Level Minimization EE 208 – Logic Design Chapter 3 Sohaib Majzoub.
Digital Logic (Karnaugh Map). Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row.
CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic 4: Cost of Logic Circuits and Karnaugh Maps José Nelson Amaral.
Karnaugh Maps (K maps).
CEC 220 Digital Circuit Design More Karnaugh Maps Monday, February 02 CEC 220 Digital Circuit Design Slide 1 of 11.
ECE 301 – Digital Electronics Minimizing Boolean Expressions using K-maps, The Minimal Cover, and Incompletely Specified Boolean Functions (Lecture #6)
Based on slides by:Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 7 – Karnaugh Maps.
1 EENG 2710 Chapter 3 Simplification of Switching Functions.
CE1110: Digital Logic Design Gate Level Minimization Karnaugh Maps (K-Maps)
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 2 – Combinational Logic Circuits Part 2.
Computer Organisation
CS 352 Introduction to Logic Design
CSCE 211: Digital Logic Design
Optimized Implementation of Logic Function
CSCE 211: Digital Logic Design
Optimized Implementation of Logic Function
CSCE 211: Digital Logic Design
CSCE 211: Digital Logic Design
CSCE 211: Digital Logic Design
ECE 331 – Digital System Design
CHAPTER 5 KARNAUGH MAPS 5.1 Minimum Forms of Switching Functions
Optimization Algorithm
SYEN 3330 Digital Systems Chapter 2 – Part 5 SYEN 3330 Digital Systems.
Chapter 3 Gate-level Minimization.
Optimized Implementation of Logic Function
CSCE 211: Digital Logic Design
COE 202: Digital Logic Design Combinational Logic Part 3
Overview Part 2 – Circuit Optimization
3-Variable K-map AB/C AB/C A’B’ A’B AB AB’
CSCE 211: Digital Logic Design
ECE 331 – Digital System Design
Presentation transcript:

Based on slides by: Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. ECE/CS 352: Digital System Fundamentals Lecture 8 – Systematic Simplification

Chapter 2 2 Outline  Four-Variable Karnaugh Maps  Systematic Simplification Prime Implicants Essential Prime Implicants  Don’t Care Entries  Prime Implicant Selection

Chapter 2 3 Four Variable Maps  Map and location of minterms: X Y Z W

Chapter 2 4 Four Variable Maps  Map and location of minterms: X Y Z W

Chapter 2 5 Four Variable Terms  Four variable maps can have rectangles corresponding to: A single 1 = 4 variables (e.g., WXYZ) A single one corresponds to a minterm Two 1s = 3 variables (e.g., X’YZ’) Four 1s = 2 variables (e.g., XZ) Eight 1s = 1 variable (e.g., W’) Sixteen 1s = zero variables (i.e., Constant "1")

Chapter 2 6 Four-Variable Maps  Example Shapes of 2-Cell Rectangles: WYZ W’X’Y’ W’XZ’ X Y Z W

Chapter 2 7 Four-Variable Maps  Example Shapes of 4-Cell Rectangles: X Y Z W X’Z’ XZ W’Y

Chapter 2 8 Four-Variable Maps  Example Shapes of 8-Cell Rectangles: X Y Z W W’ Z X’

Chapter 2 9 Four-Variable Map Simplification  )8,10,13,152,4,5,6,7, (0, Z)Y,X,F(W, m  X Y W Z XZ W’X X’Z’ F(W,X,Y,Z) = XZ + X’Z’ + W’X

Chapter ,14,15 Four-Variable Map Simplification  )(3,4,5,7,9,1 Z)Y,X,F(W, m  X Y W Z XZ WXY F(W,X,Y,Z) = XZ + W’XY’ + WXY + WY’Z + W’YZ W’XY’ W’YZ WY’Z

Chapter 2 11 Systematic Simplification  A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle with the number of squares a power of 2.  A prime implicant is called an Essential Prime Implicant if it is the only prime implicant that covers (includes) one or more minterms.  Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map.  A set of prime implicants "covers all minterms" if, for each minterm of the function, at least one prime implicant in the set of prime implicants includes the minterm.

Chapter 2 12 DB CB B D A Example of Prime Implicants  Find ALL Prime Implicants C BD CD BD Minterms covered by single prime implicant DB ESSENTIAL Prime Implicants B C D A AD BA

Chapter 2 13 Prime Implicant Practice  Find all prime implicants for: B C A D B’D’ A B’C Prime implicants are: A, B'C, and B'D’ All prime implicants are essential

Chapter 2 14 Another Example  Find all prime implicants for: Hint: There are seven prime implicants!

Chapter 2 15 Five Variable or More K-Maps  For five variable problems, we use two adjacent K-maps. It becomes harder to visualize adjacent minterms for selecting PIs. You can extend the problem to six variables by using four K-Maps. X Y Z W V = 0 X Z W V = 1 Y V’XZ VW’ WX’

Chapter 2 16  Sometimes a function table or map contains entries for which it is known : The input values for the minterm will never occur, or The output value for the minterm is not used  In these cases, the output value need not be defined  Instead, the output value is defined as a “don't care”  By placing “don't cares” ( an “x” entry) in the function table or map, the cost of the logic circuit may be lowered.  Example 1: A logic function having the binary codes for the BCD digits as its inputs. Only the codes for 0 through 9 are used. The six codes, 1010 through 1111 never occur, so the output values for these codes are “x” to represent “don’t cares.” Don't Cares in K-Maps

Chapter 2 17  Example 2: A circuit that represents a very common situation that occurs in computer design has two distinct sets of input variables: A, B, and C which take on all possible combinations, and Y which takes on values 0 or 1. and a single output Z. The circuit that receives the output Z observes it only for (A,B,C) = (1,1,1) and otherwise ignores it. Thus, Z is specified only for the combinations (A,B,C,Y) = 1110 and For these two combinations, Z = Y. For all of the 14 remaining input combinations, Z is a don’t care.  Ultimately, each “x” entry may take on either a 0 or 1 value in resulting solutions  Any minterm with value “x” need not be covered by a prime implicant. Don't Cares in K-Maps

Chapter 2 18 Example: BCD “5 or More”  Determine a function F 1 (w,x,y,z) which is defined as "5 or more" over BCD inputs, with don't cares used for the 6 non-BCD combinations: F 1 (w,x,y,z) = w + x z + x y G = 7  This is much lower in cost than F2 where the “don't cares” were treated as "0s." z w XXX XX X x y y x w yx w z x w z) y,x,F 2 (w,  xy xz w G = 12

Chapter 2 19 Product of Sums Example  Find the optimum POS solution:

Chapter 2 20 Optimization Algorithm  Find all prime implicants.  Include all essential prime implicants in the solution  Select a minimum cost set of non-essential prime implicants to cover all minterms not yet covered: Obtaining an optimum solution: See Reading Supplement 1 - More on Optimization Obtaining a good simplified solution: Use the Selection Rule

Chapter 2 21 Prime Implicant Selection Rule  Minimize the overlap among prime implicants as much as possible. In particular, in the final solution, make sure that each prime implicant selected includes at least one minterm not included in any other prime implicant selected.

Chapter 2 22 Selection Rule Example  Simplify F(A, B, C, D) given on the K- map B D A C B D A C 1 1 Essential Minterms covered by essential prime implicants Selected F(A, B, C, D) = A’B + A’CD + AC’D + B’C’D’

Chapter 2 23 Selection Rule Example with Don't Cares  Simplify F(A, B, C, D) given on the K-map. Selected Minterms covered by essential prime implicants 1 1 x x x x x 1 B D A C x x x x x 1 B D A C 1 1 Essential F(A, B, C, D) = A’B + AB’D + B’C

Chapter 2 24 Summary  Four-Variable Karnaugh Maps  Systematic Simplification Prime Implicants Essential Prime Implicants  Don’t Care Entries  Prime Implicant Selection