Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,

Slides:



Advertisements
Similar presentations
A Minimum Cost Path Search Algorithm Through Tile Obstacles Zhaoyun Xing and Russell Kao Sun Microsystems Laboratories.
Advertisements

Group: Wilber L. Duran Duo (Steve) Liu
Optimization of Placement Solutions for Routability Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li DAC’13.
Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao.
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering.
Shuai Li and Cheng-Kok Koh School of Electrical and Computer Engineering, Purdue University West Lafayette, IN, Mixed Integer Programming Models.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Congestion Driven Placement for VLSI Standard Cell Design Shawki Areibi and Zhen Yang School of Engineering, University of Guelph, Ontario, Canada December.
MCFRoute: A Detailed Router Based on Multi- Commodity Flow Method Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li.
Layer Assignment Algorithm for RLC Crosstalk Minimization Bin Liu, Yici Cai, Qiang Zhou, Xianlong Hong Tsinghua University.
38 th Design Automation Conference, Las Vegas, June 19, 2001 Creating and Exploiting Flexibility in Steiner Trees Elaheh Bozorgzadeh, Ryan Kastner, Majid.
ER UCLA UCLA ICCAD: November 5, 2000 Predictable Routing Ryan Kastner, Elaheh Borzorgzadeh, and Majid Sarrafzadeh ER Group Dept. of Computer Science UCLA.
VLSI Routing. Routing Problem  Given a placement, and a fixed number of metal layers, find a valid pattern of horizontal and vertical wires that connect.
Routing 1 Outline –What is Routing? –Why Routing? –Routing Algorithms Overview –Global Routing –Detail Routing –Shortest Path Algorithms Goal –Understand.
1 Efficient Placement and Dispatch of Sensors in a Wireless Sensor Network Prof. Yu-Chee Tseng Department of Computer Science National Chiao-Tung University.
Triple Patterning Aware Detailed Placement With Constrained Pattern Assignment Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D.F. Wong.
A Resource-level Parallel Approach for Global-routing-based Routing Congestion Estimation and a Method to Quantify Estimation Accuracy Wen-Hao Liu, Zhen-Yu.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
POLAR 2.0: An Effective Routability-Driven Placer Chris Chu Tao Lin.
Constrained Pattern Assignment for Standard Cell Based Triple Patterning Lithography H. Tian, Y. Du, H. Zhang, Z. Xiao, M. D.F. Wong Department of ECE,
Hsiu-Yu Lai Ting-Chi Wang A TPL-Friendly Legalizer for Standard Cell Based Design SASIMI ‘15.
Cost-Based Tradeoff Analysis of Standard Cell Designs Peng Li Pranab K. Nag Wojciech Maly Electrical and Computer Engineering Carnegie Mellon University.
Routing 2 Outline –Maze Routing –Line Probe Routing –Channel Routing Goal –Understand maze routing –Understand line probe routing.
General Routing Overview and Channel Routing
Chih-Hung Lin, Kai-Cheng Wei VLSI CAD 2008
Introduction to Routing. The Routing Problem Apply after placement Input: –Netlist –Timing budget for, typically, critical nets –Locations of blocks and.
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
Global Routing. Global routing:  To route all the nets, should consider capacities  Sequential −One net at a time  Concurrent −Order-independent 2.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
CRISP: Congestion Reduction by Iterated Spreading during Placement Jarrod A. Roy†‡, Natarajan Viswanathan‡, Gi-Joon Nam‡, Charles J. Alpert‡ and Igor L.
Global Routing.
1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.
Solving Hard Instances of FPGA Routing with a Congestion-Optimal Restrained-Norm Path Search Space Keith So School of Computer Science and Engineering.
1 Global Routing Method for 2-Layer Ball Grid Array Packages Yukiko Kubo*, Atsushi Takahashi** * The University of Kitakyushu ** Tokyo Institute of Technology.
Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture.
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 5: Global Routing © KLMH Lienig 1 EECS 527 Paper Presentation High-Performance.
Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.
BSG-Route: A Length-Matching Router for General Topology T. Yan and M. D. F. Wong University of Illinois at Urbana-Champaign ICCAD 2008.
New Modeling Techniques for the Global Routing Problem Anthony Vannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo,
Efficient Multi-Layer Obstacle- Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu,Meng-Xiang Li, Yao-Wen Chang.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
AUTOMATIC BUS PLANNER FOR DENSE PCBS Hui Kong, Tan Yan and Martin D.F. Wong Department of Electrical and Computer Engineering, University of Illinois at.
Jason Cong‡†, Guojie Luo*†, Kalliopi Tsota‡, and Bingjun Xiao‡ ‡Computer Science Department, University of California, Los Angeles, USA *School of Electrical.
IO CONNECTION ASSIGNMENT AND RDL ROUTING FOR FLIP-CHIP DESIGNS Jin-Tai Yan, Zhi-Wei Chen 1 ASPDAC.2009.
GLARE: Global and Local Wiring Aware Routability Evaluation Yaoguang Wei1, Cliff Sze, Natarajan Viswanathan, Zhuo Li, Charles J. Alpert, Lakshmi Reddy,
ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM Muhammet Mustafa Ozdal, Martin D. F. Wong ICCAD ’ 07.
The Application of The Improved Hybrid Ant Colony Algorithm in Vehicle Routing Optimization Problem International Conference on Future Computer and Communication,
A Negotiated Congestion based Router for Simultaneous Escape Routing Q.Ma, T.Yan and Martin D.F. Wong Department of Electrical and Computer Engineering.
Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng NTU &Synopsys An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs.
An Efficient Linear Time Triple Patterning Solver Haitong Tian Hongbo Zhang Zigang Xiao Martin D.F. Wong ASP-DAC’15.
ECE 260B – CSE 241A /UCB EECS Kahng/Keutzer/Newton Physical Design Flow Read Netlist Initial Placement Placement Improvement Cost Estimation Routing.
PARR:Pin Access Planning and Regular Routing for Self-Aligned Double Patterning XIAOQING XU BEI YU JHIH-RONG GAO CHE-LUN HSU DAVID Z. PAN DAC’15.
ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
Routability-driven Floorplanning With Buffer Planning Chiu Wing Sham Evangeline F. Y. Young Department of Computer Science & Engineering The Chinese University.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
High-Performance Global Routing with Fast Overflow Reduction Huang-Yu Chen, Chin-Hsiung Hsu, and Yao-Wen Chang National Taiwan University Taiwan.
An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.
Congestion-Driven Re-Clustering for Low-cost FPGAs MASc Examination Darius Chiu Supervisor: Dr. Guy Lemieux University of British Columbia Department of.
XGRouter: high-quality global router in X-architecture with particle swarm optimization Frontiers of Computer Science, 2015, 9(4):576–594 Genggeng LIU,
VLSI Physical Design Automation
2 University of California, Los Angeles
Jin-Yih Li Yih-Lang Li Computer & Information TSMC Science Department,
Performance Optimization Global Routing with RLC Crosstalk Constraints
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering, Purdue University A Fast Maze-Free Routing Congestion Estimator With Hybrid Unilateral Monotonic Routing ICCAD’12

Introduction Problem Description Unilateral Monotonic Routing Design Flow of RCE Experimental Results Conclusions Outline 2

Considering the routability issue in placement stage can avoid generating an unroutable design. Performs global routing to analyze routing congestion can identify more precisely the congestion information than the probabilistic method. –But slower Maze routing with A* search scheme is the indispensable kernel algorithm of state- of-the-art global routers However, maze routing is slower than other routing algorithms, such as pattern routing and monotonic routing algorithms. Introduction 3

This work develops an extremely fast global router without invoking maze routing to achieve competitive routing quality as an ideal built-in routing congestion estimator (RCE) for placers. Two efficient routing algorithms, called unilateral monotonic routing and hybrid unilateral monotonic (HUM) routing. An efficient congestion-aware bounding box expansion scheme. –can improve runtime by 50% than without this scheme. Introduction 4

Global routing is formulated as the routing problem on a grid graph G(V, E), where V denotes the set of grid cells, and E refers to the set of grid edges. The layout is typically partitioned into an array of global cells (G-cells). Each grid edge is termed by the proximity of the related G-cells to its two end nodes. Problem Description 5 Global bins Cells Global edges Global bins Global edges

The capacity c(e) of a grid edge e indicates the number of routing tracks that can legally cross the abutting boundary. The number of wires that pass through grid edge e is called the demand of the grid edge d(e). The overflow of a grid edge e is defined as where w L and s L respectively denote the minimum wire width and wire spacing at layer L where e belongs. Problem Description 6

Overflow minimization has a higher priority than runtime improvement for global routing that offers a global path to guide the detailed routing of each net. The runtime issue become critical because the estimator have to report the congestion information to placers in a limited time budget (e.g. around 1~5 min). This work focuses on comply with the limited time budget for the global routing in all benchmarks. Problem Description 7

Unilateral monotonic routing identifies a least-cost routing path within a limited region using minimal horizontal or vertical distance. Definition. Horizontally/Vertically monotonic (HM/VM) routing identifies the least-cost routing path from the source to the target using minimal horizontal/vertical distance. For a HM/VM routing path, a detour occurs only in vertical/horizontal move. Unilateral Monotonic Routing 8 Vertically Monotonic routing path Horizontally Monotonic routing path routing path combining vertically and horizontally monotonic routing

Unilateral Monotonic Routing 9 B : window lc(u) : least-cost of node u cost(u,v) : routing cost of the edge e(u,v) d(u) : least-cost of the VM/HM routing path within b from s to u π(u) :the predecessor of u Two Stage First Stage –Simple sequential examination initiating from the start node towards the left and right boundaries of B Second Stage –Phase 1 : Determines the least-cost VM path to connect every node from the start node at the left or bottom side –Phase 2 : Determines the least-cost VM path to connect every node from the start node at the right side

10 Unilateral Monotonic Routing Calculate the least cost of the VM paths from s to each node v(i,y 1 ) for b.l ≤i ≤ b.r Determines the least-cost VM path to connect every node from the start node at the left or bottom side determines the least- cost VM path to connect every node from the start node at the right side

Unilateral Monotonic Routing 11 A congestion map The routing model Line 1-9 The predecessor of each node u in the row of y-coordinate y 1 after d(u) is obtained Line The predecessor of each node u in the row of y-coordinate y1+1 after lc lb (u) is obtained Line the predecessor of each node u in the row of y-coordinate y 1+1 after d(u) is obtained The routing result of VM routing

Hybrid Unilateral Monotonic Routing 12

Congestion-Aware Bounding Box Expansion Traditional box expansion chooses to expand the bounding box along both x and y coordinates to resolve the overflow. However, the bounding box only needs to expand horizontally in Fig. (a) This could occur frequently during routing. Based on this observation, this work presents a novel congestion-aware bounding box expansion scheme to avoid over expanding. Unilateral Monotonic Routing 13

Congestion-Aware Bounding Box Expansion Before rerouting a net, this work analyzes the amount of horizontal overflowed grid edges (HOEs) and vertical overflowed grid edges (VOEs) by tracing the routing path of the rerouted net. If the number of HOEs is more than that of VOEs, the bounding box expands vertically by δ units. Based on the assumption that two opposite sides have different congestion states, extending the side near the congested region may be unnecessary, implying that the extension of each boundary of B should be discussed separately. Unilateral Monotonic Routing 14

(the left boundary of B is used to illustrate the concept) where V L denotes the set of grid nodes on the left boundary of B; d(s,v) and d(t,u) represent the least cost of the unilateral monotonic routing paths from s to v and from t to u, respectively. manh(v,u) refers to the Manhattan distance between v and u. α is the lower-bound routing cost of a grid edge. Congestion-Aware Bounding Box Expansion 15

Design Flow of RCE 16 In the rip-up and rerouting stage, before net n i is rerouted, the bounding box of n i is expanded according to the proposed congestion-aware expansion scheme. For a situation in which the width of the bounding box is equal to the x-distance between the source and the target of n i, n i is rerouted using HM routing. If the height of the bounding box is equal to the y-distance between the source and the target of n i, n i is rerouted using VM routing. Otherwise, n i is rerouted by HUM routing.

Experimental Results 17

Experimental Results 18

This work presents two efficient routing algorithms, unilateral monotonic routing and HUM routing. A congestion-aware bounding box expansion scheme is developed to avoid over expanding bounding boxes. Based on these contributions, a maze-free router is developed, capable of achieving 2.75X to 26.83X speedup than NCTUgr2. Conclusions 19