10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Targeting Tiled Architectures in Design Exploration Lilian Bossuet 1, Wayne Burleson 2, Guy Gogniat 1, Vikas Anand 2, Andrew Laffely 2, Jean-Luc Philippe 1 1 LESTER Lab Université de Bretagne Sud Lorient, France {lilian.bossuet, guy.gogniat, 2 Department of Electrical and Computer Engineering University of Massachusetts, Amherst, USA {burleson, vanand,

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Space Exploration u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space Exploration: Motivations u Design solutions for new telecommunication and multimedia applications targeting embedded systems u Optimization and reduction of SoC power consumption u Increase computing performance è Increase parallelism è Increase speed u Be flexible è Take into account run-time reconfiguration è Targeting multi-granularity (heterogeneous) architectures

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space Exploration: Flow u Progressive design space reduction: è iterative exploration è refinement of architecture model  increase of performance estimation accuracy u One level of abstraction for one level of estimation accuracy

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Works

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Reconfigurable Architectures u Bridging the flexibility gap between ASICs and microprocessor [Hartenstein DATE 2001] u Energy efficient and solution to low power programmable DSP [Rabaey ICASSP 1997, FPL 2000] u Run Time Reconfigurable [Compton & Hauck 1999] u => A key ingredient for future silicon platforms [Schaumont & all. DAC 2001]

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space of Reconfigurable Architecture RECONFIGURABLE ARCHITECTURES (R-SOC) FINE GRAIN (FPGA) MULTI GRANULARITY (Heterogeneous) COARSE GRAIN (Systolic) Processor + Coprocessor Tile-Based Architecture Coarse Grain Coprocessor Fine Grain Coprocessor Island Topology Hierarchical Topology Linear Topology Hierarchical Topology Mesh Topology Chameleon REMARC Morphosys Pleiades Garp FIPSOC Triscend E5 Triscend A7 Xilinx Virtex-II Pro Altera Excalibur Atmel FPSIC Xilinx Virtex Xilinx Spartran Atmel AT40K Lattice ispXPGA Altera Stratix Altera Apex Altera Cyclone Systolic Ring RaPiD PipeRench DART FPFA RAW CHESS MATRIX KressArray Systolix Pulsedsp aSoC E-FPFA

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Works

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 A Target Architecture: aSoC u Adaptive System-on-a-Chip (aSoC) u Tiled architecture containing many heterogeneous processing cores (RISC, DSP, FPGA, Motion Estimation, Viterbi Decoder) u Mesh communication network controlled with statically determined communication schedule u A scalable architecture.

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 tile FPGA uProc MUL u Heterogeneous Cores aSoC Architecture u Point-to-point connections ctrl SouthCore West North East u Communication Interface

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Communications Interface Core Coreports Decoder Local Frequency & Voltage North to South & East Instruction Memory PC Controller North South East West LocalConfig. North South East West Inputs Outputs u Interface Crossbar è inter-tile transfer è tile to core transfer u Interconnect/Instruction Memory è contains instructions to configure the interface crossbar (cycle-by- cycle) u Interface Controller è selects the instruction u Coreports è data interface and storage for transfers with the tile IP core u Dynamic Voltage and Frequency Selection è Dynamic Power Management Interface Crossbar

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Exploration... u Type of tiles u Number of each type of tile u Placement of the tiles u Intern architecture of reconfigurable tiles (FPGA core) u Communication scheduling

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Space Exploration: Goals u Goal: Rapid exploration of various architectural solutions to be implemented on heterogeneous reconfigurable architectures (aSoC) in order to select the most efficient architecture for one or several applications u Take place before architectural synthesis (algorithmic specification with high level abstraction language) u Estimations are based on a functional architecture model (generic, technology-independent) u Iterative exploration flow to progressively refine the architecture definition, from a coarse model to a dedicated model

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Design Exploration Flow Targeting Tiled Architecture

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Application Analysis u Use of algorithmic metrics and dedicated scheduling algorithms to highlight the target architectures u Algorithmic metrics: è Characterize the application orientation Processing Memory Control è Characterize the application potential parallelism Processing Memory

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Tile Exploration: with 3 steps u Projection: è Link between necessary resources (application) and available resources (tile) è Use of an allocation algorithm based on communication costs reduction u Composition: è Take into account of the function scheduling to estimate additional resources (register, mux, …) u Estimation: è performance interval computation (lower and upper bounds) è speed/resource utilization/power characterization

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Builder u Environment AppMapper u Partition and assignment è based on Run Time Estimation u Compilation è Communication Scheduling è Core compilation u Generate tiles configuration è Communications instructions è Bitstreams (for reconfigurable tile) è RISC instructions

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 aSoC Analysis u Use the results of previous steps è Functions scheduling è Tile allocation è Communication scheduling u Complete estimation of the proposed solution è Global execution time è Global power consumption è Total area

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Results u aSoC architecture (UMASS) è Prototype of aSoC interconnect Technology 0.18 µm Clock speed of 400 MHz u AppMapper (UMASS) è Several mapped applications Matrix operations Median Filter Viterbi decoder DCT u Tile exploration (UBS) è Application analysis Intelligent Camera (motion detection) Matching Pursuit è Projection step Lee DCT Matrix operations

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Outline u Introduction: Design Exploration Flow Principe u Design Space of Reconfigurable Architecture u A Target Architecture: aSoC u Proposition of Design Space Exploration Flow u Results u Conclusion and Future Work

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Conclusion and future work u Conclusion è Original design exploration flow working at a high level of abstraction è Fast and flexible (use of functional view of the architectures) è Targeting an efficient reconfigurable architecture: aSoC è Statically-scheduled, point-to-point communications u Future Work è Development of larger set of design exploration benchmarks è Exploration of other configurable systems

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Thank you...

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Previous Work u Xplorer - University of Kaiserslautern, Germany [Hartenstein PATMOS 2000] è Targets a mesh coarse grain architecture: The KressArray a fast reconfigurable ALUs è Gives design guidance concerning: the size of the array, the available operators, the communication architecture and the connection structure. è Controlled by performance and power estimations. è Starts with high level specification of application (ALE-X language). u RAW - Massachusetts Institute of Technology, USA [Moritz FCCM 1998] è Targets a reminiscent coarse grained FPGA: The MIT Raw Microprocessor è Answers to the balance problem: to determine the best division of VLSI resources among computing, memory and communication. è Answers to the grain problem: to determine the optimum size of each architecture tiles è Use several models: architecture model, costs model and performance model

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 HCDFG: Hierarchical Control Data Flow Graph Task 1Task 2 Task 1 F2 F1 F5 F4 F3 HCDFG HDFG LOOP DFG CDFG DFG Loop CORE X Y# C Y MAC ALU A

10th Reconfigurable Architecture Workshop, RAW’03, Nice, France, Tuesday, April 22, 2003 Application’s Metrics Average Parallelism metric (a lot of parallelism if γ is high) Nb of global memory accesses and processing operations Critical Path γ = Nb of global memory accesses Nb of processing operations + Nb of global memory accesses MOM = Memory Orientation Metric [0,1] Nb of test Nb of global mem. accesses + Nb of proc. op. + Nb of test COM = Control Orientation Metric [0,1] Y. Le Moullec, N. Ben Amor, J-Ph. Diguet, M. Abid and J-L. Philippe. Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. In DATE 2002, Munich, Germany, March 2002