MTVV Automated tests generation from SysML models July 1st Jonathan Lasalle

218 juillet 2015 Outline Test Designer VETESS project SysML/SysML4MBT Test Generation Strategies Conclusion and future works

318 juillet 2015 Test Designer PIVOT FILE UML Java TEST MODEL UML4ST RSM Test Designer™ Tests

418 juillet 2015 Example : front lightings Vehicle front lightings Management (HighLights + HeadLights) Actions : Turn on/off HighLights Turn on/off HeadLights 4 possible states : All Lights OFF HighLights Only HeadLights Only All Lights ON

518 juillet 2015 UML4ST (UML for Smartesting) 1 class diagram (static view) 1 object diagram (representation of the initial state of the system)

618 juillet 2015 UML4ST (UML for Smartesting) 1 statemachine diagram (dynamic view) Trigger : Operation Call Guard : Boolean expression (OCL) Action : OCL expression

718 juillet 2015 Outline Test Designer VETESS project SysML/SysML4MBT Test Generation Strategies Conclusion and future works

818 juillet 2015 VETESS project VETESS = Vérification de systèmes embarqués VEhicule par génération automatique de TESts à partir des Spécifications Project labelized by the Competitiveness Cluster «Véhicule du Futur» (2008/2010) Project members : Smartesting : editor of MBT’s software (Test Designer) Clemessy : concepteur de bancs de validation PSA : car manufacturer LIFC : Model Based Testing experience (MBT) MIPS : Model Driven Engineering experience (MDE)

918 juillet 2015 VETESS project Specification of systems under test (SUT) with SysML behavioral models Automated tests generation from SysML models with Test Designer (Smartesting) Export and execution of tests on TestInView platform (Clemessy) Automation of this process with a tools framework which contains those parts.

1018 juillet 2015 Tools framework TEST MODEL SysML4MBT PAPYRUS UML4ST MetaModel SysML4MBT Metamodel PIVOT FILE UML Java TEST MODEL UML4ST PAPYRUS TEST MODEL UML4ST RSM Test Designer ™ Tests Embedded Dedicated tests Adaptation layer (TestInView Library) + +

1118 juillet 2015 Scientific challenge To consider models with parallelism Reactive systems (Transmission of Signals) To consider the system and his environment Test Generation strategies dedicated to those problematics

1218 juillet 2015 Outline Test Designer VETESS project SysML/SysML4MBT Test Generation Strategies Conclusion and future works

1318 juillet 2015 SysML System Modeling Language Modeling language for system engineering Subset of UML with extensions OMG : SysML 1.0 since September 2007 SysML = UML profile Fit to modeling embedded system

1418 juillet 2015 SysML diagrams Diagrams in both : Use-Case diagram Sequence diagram Activity diagram State Machine diagram Package diagram Variation of UML : Class diagram => Block diagram Composite Structure diagram => Internal Block diagram Only on SysML Parametric diagram : physics equations Requirement diagram

1518 juillet 2015 SysML4MBT : block diagram 1 block diagram => static view

1618 juillet 2015 SysML4MBT : block diagram Flow ports : Controller  outActionHead  outActionHigh HeadLights  inActionHead HighLights  inActionHigh

1718 juillet 2015 SysML4MBT : internal block diag. 1 internal block diagram => interconnections between blocks

1818 juillet 2015 SysML4MBT : state machine diag. 1 or more statemachine diagram(s) => dynamic view of system parts SEND 1 RECEIVE 1 SEND 1 SEND 2 SEND 3 SEND 4 RECEIVE 4 RECEIVE 3 RECEIVE 2

1918 juillet 2015 Scientific challenge To consider models with parallelism Reactive systems (Transmission of Signals) To consider the system and his environment Test Generation strategies dedicated to those problematics OK => Several state machine diagrams OK => ports + signal OK => Several state machine diagrams

2018 juillet 2015 Outline Test Designer VETESS project SysML/SysML4MBT Test Generation Strategies Conclusion and future works

2118 juillet 2015 Test Generation Strategy : TD Test Designer All behaviors For each behavior => 1 test case which passes through the behavior Action of a transition: IF (BOOL) THEN Action A Else Action B TEST 1 (with BOOL = true) TEST 2 (with BOOL = false)

2218 juillet 2015 Test Generation Strategy : DUvar Uses state variables For each variable Var For each behavior B1 which defines Var (Var = 5)  For each behavior B2 which uses Var (Var2 = Var) –B1/B2 is a pair Criteria : All_Uses : Coverage of each pair B1/B2 (1 path) All_Def_Use_Paths : Coverage of all paths for each pair B1/B2

2318 juillet 2015 Test Generation Strategy : ComCover Uses connectors For each connector Connect For each Behavior B1 which sends signal on Connect  For each Behavior B2 which receives signal sent by B1 –B1/B2 is a pair Criteria All_Receives : Coverage of each pair B1/B2 (1 path) All_Send_Receive_Paths : Coverage of all paths for each pair B1/B2

2418 juillet 2015 Test Generation Strategy : Scenario Scenarios defined by the user 3 ideas: With valuated paths  Ex : CallOp1(5), CallOp2(4), CallOp1(8) With not-valuated paths :  Ex : CallOp1(?), CallOp2(?), CallOp1(5) With not-valuated not-complete paths :  Ex : CallOp1(?), ?, CallOp2(6)

Experimentations FrontLightingsFrontWiper (manual) Nb statemachine36 Nb states(4,2,2)(1,1,1,1,14,2) Nb transitions(8,2,2)(2,2,2,1,20,3) Nb tests algo TD1230 Coverage Algo TDAll_transitions Nb tests DUvar015 Coverage All_UsesNone Nb tests ComCover813 Coverage All_ReceivesDU-PATHSNone Coverage DUvar+ComCover DU-PATHS 2518 juillet 2015

2618 juillet 2015 Outline Test Designer VETESS project SysML/SysML4MBT Test Generation Strategies Conclusion and future works

2718 juillet 2015 Conclusion & Outlook TEST MODEL SysML4MBT PAPYRUS UML4ST MetaModel SysML4MBT Metamodel PIVOT FILE UML Java TEST MODEL UML4ST PAPYRUS TEST MODEL UML4ST RSM Test Designer ™ Tests Embedded Dedicated tests Adaptation layer (TestInView Library) + + DUvar ComCover Scenario

The End Questions? 2818 juillet 2015