Towards ideal codes: looking for new turbo code schemes Ph.D student: D. Kbaier Ben Ismail Supervisor: C. Douillard Co-supervisor: S. Kerouédan

What is a good code? Ideal system Limits to the correction capability of any code Established by Shannon Good convergence Error rate greatly decreases close to the theoretical limit Waterfall region High asymptotic gain Search for the ideal encoder/decoder pair Dilemma: good convergence versus high MHD Ph.D defense, Monday 26th September 2011

Turbo codes Ph.D defense, Monday 26th September 2011 http://www-elec.enst-bretagne.fr/demos/principe/turbo_codes.html Ph.D defense, Monday 26th September 2011

Constraints on λ Extract from my Ph.D report: Ph.D defense, Monday 26th September 2011

Choice of the post-encoder Influences performance in both the waterfall and error floor region Must be simple low memory RSC codes The code is made tail biting  accumulator Must not exhibit too much error amplification EXIT analysis Ph.D defense, Monday 26th September 2011

Choice of the post-encoder k = 1146 bits R = 2/3 λ = 1/4 MAP, 10 iterations Ph.D defense, Monday 26th September 2011

Simulated performance of the 3D TC with random and regular interleavers Π’ Regular permutation: Achieves the maximum value of the spread Performs better than the random interleaver k = 762 bits R = 1/2 λ = 1/8 Ph.D defense, Monday 26th September 2011 k = 762 bits k = 762 bits λ = 1/8

Performance of 3GPP2 based 3D TCs Ph.D defense, Monday 26th September 2011

Relation between λ and dmin Extract from my Ph.D report pages 38-39: The authors in [63, 64] analyzed the asymptotic weight distribution of 3D TCs and showed that their typical minimum distance may, depending on certain parameters, asymptotically grow linearly with the block length. Ph.D defense, Monday 26th September 2011

Relation between λ and dmin Ph.D defense, Monday 26th September 2011

3D TCs hardware implementation issues: decoder architecture and complexity analysis 3D turbo decoder architecture: Input module Double input buffer Input buffer divided into as many MBs as P Parallelism  different throughputs Decoder module P SISO processors & an extrinsic memory Performs I iterations on the frame stored in the input module Writes the decoded codeword into the output module Output module Stores the hard decisions produced by the decoder module Sends them to the output of the decoder No parallelism is considered for the predecoder The predecoder has much less data to process than the main SISO decoders Only λ = 1/4 or λ = 1/8 of the parity bits are reencoded Ph.D defense, Monday 26th September 2011

Typical overall 3D turbo decoder architecture Decoded bits MBP-1 MB0 MB1 Input module SISOP-1 SISO1 SISO0 Extrinsic memory (syste- matic) Main decoder module Input samples Output module Extrinsic memory (parity) PREDEC SISO Pre-decoder module Ph.D defense, Monday 26th September 2011

Max-Log-MAP decoder complexity analysis Arithmetic and logical operations Branch metrics Forward and backward state metrics Soft and hard decisions Extrinsic information related to information bits Extrinsic LLRs related to redundancy bits Ph.D defense, Monday 26th September 2011

Memory requirements for the 3D turbo decoder The amount of RAM and ROM memory TC permutation parameters  small amount of ROM memory For the RAM memory: 2 input buffers for each data sequence Including systematic and parity bits Stemming from the transmission channel RAM to store the extrinsics Additional extrinsics for the 3D TC RAM to store the hardware decision at decoder output Inside the SISO decoding process, state metrics have to be stored at each iteration Ph.D defense, Monday 26th September 2011

Optimization method Ph.D defense, Monday 26th September 2011

Optimization results for k = 1530 data bits λ = 1/8 Before optimization d 18 20 21 22 23 24 25 η(d) 1 4 2 6 After optimization d 20 21 22 … η(d) 1 3 2 ... Total increase in dmin by + 42 %  a gain of 2.5 decades in the error floor Max-Log-MAP, 10 iterations Ph.D defense, Monday 26th September 2011

Optimization results for k = 1146 data bits λ = 1/4 Ones concentrated in the systematic part at addresses {586, 587, 591, 650, 651,655, 763, 764, 768, 1019, 1020, 1024} Modification: {585, 587, 650, 651, 763 and 764} instead of {9, 101, 581, 925, 1029 and 1133} The new minimum distance of the optimized 3D TC is 33 (compared to 7) Distance 12 15 21 27 Multiplicity 1 3 ≥1 ≥2 x Y1 Y2 Address 5 Address 13 Address 1 Address 9 Ph.D defense, Monday 26th September 2011

EXIT chart analysis: convergence threshold of the 3D TC EXIT chart based convergence analysis: Determination of the convergence threshold of the TC & 3D TC (1.49 for an 8-state binary TC and R =2/3) Compute the loss of convergence Larger λ  more significant loss EXIT chart of the 3D TC with λ = 1/8 at Eb/N0=1.5 dB for code rate R = 2/3 EXIT chart of the 3D TC with λ = 1/8 at Eb/N0=1.55 dB for code rate R = 2/3 Ph.D defense, Monday 26th September 2011

Here Eb/N0 =1.57 dB < convergence threshold EXIT chart analysis: convergence threshold of the time varying 3D TC(1/2) R = 2/3 λ = 1/4 Eb/N0=1.57 dB Here Eb/N0 =1.57 dB < convergence threshold Ph.D defense, Monday 26th September 2011

Convergence threshold:1.58 dB EXIT chart analysis: convergence threshold of the time varying 3D TC(2/2) R = 2/3 λ = 1/4 Eb/N0=1.58 dB Convergence threshold:1.58 dB Ph.D defense, Monday 26th September 2011

Error rate performance of time varying 3D TCs Time varying results for blocks of k = 1146 bits Transmission over AWGN channel Loss of convergence reduced by 50% from 0:18 dB to 0:09 dB Ph.D defense, Monday 26th September 2011

An optimal value of L using EXIT charts? Ph.D defense, Monday 26th September 2011

An optimal value of L using EXIT charts? Eb/N0=1.6 dB Ph.D defense, Monday 26th September 2011

3D TCs for high spectral efficiency transmissions Transmission scheme BICM approach Among the bits forming a symbol in M-QAM or M-PSK modulations, the average probability of error is not the same for all the bits Three constellation mappings: Mapping uniformly distributed on the entire constellation Systematic bits mapped to better protected places as a priority Systematic bits (then if possible) post-encoded parity bits protected as a priority Ph.D defense, Monday 26th September 2011

Example: 3D TCs associated with an 8-PSK modulator 3 bits of an 8-PSK symbol 573 8-PSK symbols R = 4/5 λ = 1/8 The third configuration cannot be adopted Systematic bits mapped to better protected places Significant gain: 0.5 dB k = 1146 bits 1146 x 143 y1 143 y2 288 w Ph.D defense, Monday 26th September 2011

Decoding of irregular TCs Only one SISO The decoder computes the channel output LLRs Appropriate repetition to each LLR A posteriori probability Extrinsic information = product of d-1 extrinsics Appropriate likelihoods repetition SISO Decoder Systematic part Channel output APP Π Product of Extrinsic information Ph.D defense, Monday 26th September 2011

Monte Carlo simulations Fixing a degree dIrreg and varying its fraction fIrreg A fraction that achieves the best performance can be found Changing the degree dIrreg , while the fraction is fixed to the value already selected We can then find optimal values for both dIrreg and fIrreg This profile is not automatically the best one: Optimization does not take into account all the possible combinations (dIrreg , fIrreg) Better performance may be attained when the profile is not restricted to two non-zero fractions Monte Carlo simulations are time consuming We propose a method based on the EXIT diagrams to select a good degree profile Ph.D defense, Monday 26th September 2011

Determination of the degree profile using hierarchical EXIT charts Plot the EXIT diagrams for a finite block length Why? For infinite block lengths All the curves merge with one another  We cannot distinguish between the different degree profiles For finite block sizes EXIT tool adapted Hierarchy between the different degree profiles Hypothesis: extrinsic information messages are i.i.d The aim is not to compute accurate convergence thresholds The method Simple Comparing many degree profiles at the same time Even profiles with more than two non-zero fractions Ph.D defense, Monday 26th September 2011

Determination of the degree profile using hierarchical EXIT charts Ph.D defense, Monday 26th September 2011

Determination of the degree profile using hierarchical EXIT charts Ph.D defense, Monday 26th September 2011

Performance of irregular TCs Irregular TCs can achieve performance closer to capacity But very poor asymptotic performance Only one reference [1] deals with the problem of lowering the error floor of irregular TCs No previous work focused on optimizing the interleaver except in [2] Our interest: Not only large block lengths But also medium and short blocks Proposed solutions in [1,2] do not seem concrete Especially if only few iterations are required during the decoding process [1] H. Sawaya and J. Boutros. “Irregular turbo-codes with symbol-based iterative decoding”, 3rd International Symposium on Turbo-codes, Brest, France, September 2003. [2] G. M. Kraidy and V. Savin, “Capacity-approaching irregular turbo codes for the binary erasure channel,” IEEE Trans. Com., vol. 58, no. 9, pp. 2516–2524, September 2010. Ph.D defense, Monday 26th September 2011

How to devise sophisticated permutations for irregular TCs? Example: Degree profile (f2,f8) f2 = 5/6 and f8 = 1/6 First idea: all the groups of 8 bits are uniformly distributed To avoid correlation  large spread between the pilot groups Empirical value for the spread: Constraint on f8: page 31 Ph.D defense, Monday 26th September 2011 31

Ph.D defense, Monday 26th September 2011

Performance of irregular TCs with post-encoding All simulations use the MAP algorithm with 10 decoding iterations Degree profile (f2,f8), dav = 3, R = ¼ and k = 2046 bits 3GPP2 interleaver, interleaver size: 6138 Ph.D defense, Monday 26th September 2011