HIGH LEVEL SYNTHESIS WITH AREA CONSTRAINTS FOR FPGA DESIGNES: AN EVOLUTIONARY APPROACH Tesi di Laurea di: Christian Pilato Matr.n Relatore: Prof. Fabrizio FERRANDI Correlatore: Ing. Antonino TUMEO

C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Index Introduction to HLS and RA Traditional Approach to Register Allocation Proposed Solution to Register Allocation Transitive Reduction of SDG Improved Dataflow Analysis Conflict Graph Creation Choose of the Best Algorithm Conclusion

Introduction to HLS C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Scheduling Allocation Register Allocation Module Allocation Binding

Register Allocation C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Problem definition: find a solution to register allocation function V s : values that have to be stored M s : set of storage modules (registers and register files) Goal: minimize the number of storage modules

Traditional Approach C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Compatibility graph w(v): cycle step in which the storage value v is written P(v): last cycle step in which the storage value v is read operator ║: returns true if two intervals overlap and return false otherwise Clique covering

Proposed Approach C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Transitive Reduction of SDG Dataflow Analysis Conflict Graph Creation Choose of the Best Algorithm

Transitive Reduction of SDG C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Original relation graph Reduced graph Transitive reduction of a graph is referred to be the minimal representation of graph flows The proposed solution provides an improved implementation of a depth-first search-based algorithm for finding the transitive reduction of a directed graph

Dataflow Analysis C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Dataflow equations used to calculate liveness information: Two steps: 1.Find by iteration a solution to these equations (backward analysis) 2.Clean unuseful information (forward analysis)

Conflict Graph Creation C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ For every edge into the control flow graph If source vertex and target one are scheduled into different control step, a register is needed for each variable living out from the source vertex to keep value alive until target one will use it Then a conflict edge must be set between each pair of variable in this situation, because they cannot use the same storage module There is no conflict in case of: Alias: Mutual exclusion

Choose of the Best Algorithm C. Pilato and F. Malcotti – Politecnico di Milano 04/10/

Conclusions C. Pilato and F. Malcotti – Politecnico di Milano 04/10/ Good results in terms of storage modules number can be obtained using the traditional approach Improved analysis can lead to a better conflict graph, and then to a further reduced number of storage units implied The new approach can substitute and improve the traditional register allocation solution in PandA framework

Thank you! C. Pilato and F. Malcotti – Politecnico di Milano 04/10/