Cosc 2150: Computer Organization

Slides:



Advertisements
Similar presentations
Computer Science Education
Advertisements

SE 292 (3:0) High Performance Computing L2: Basic Computer Organization R. Govindarajan
Chapter 4 The Von Neumann Model
Chapter 4 The Von Neumann Model
1 Patt and Patel Ch. 7 LC-3 Assembly Language. 2 LC-3 is a load/store RISC architecture Has 8 general registersHas 8 general registers Has a flat 16-bit.
Slides created by: Professor Ian G. Harris Efficient C Code  Your C program is not exactly what is executed  Machine code is specific to each ucontroller.
ARM versions ARM architecture has been extended over several versions.
Overheads for Computers as Components 2nd ed.
CPSC 330 Fall 1999 HW #1 Assigned September 1, 1999 Due September 8, 1999 Submit in class Use a word processor (although you may hand-draw answers to Problems.
Stored Program Architecture
Assembly Language.
MIPS Assembly Tutorial
Chapter 5 The LC-3.
ITEC 352 Lecture 13 ISA(4).
1 Lecture 3: MIPS Instruction Set Today’s topic:  More MIPS instructions  Procedure call/return Reminder: Assignment 1 is on the class web-page (due.
Goal: Write Programs in Assembly
Cosc 2150 Arrays in assembly code. Variables and addresses Uncompiled ld [a], %r1 addcc %r1, 2, %r3 ARC has three addressing modes —immediate, direct,
ITEC 352 Lecture 14 ISA(5). Review Questions? Exam 1 next Friday Assembly –Assembler –Basic structure –Registers –Memory.
1/1/ / faculty of Electrical Engineering eindhoven university of technology Introduction Part 2: Data types and addressing modes dr.ir. A.C. Verschueren.
The 8051 Microcontroller and Embedded Systems
Machine Instructions Operations 1 ITCS 3181 Logic and Computer Systems 2015 B. Wilkinson Slides4-1.ppt Modification date: March 18, 2015.
CHAPTER 4 COMPUTER SYSTEM – Von Neumann Model
1 ICS 51 Introductory Computer Organization Fall 2006 updated: Oct. 2, 2006.
By Tien Phung CS 147 Dr. Sin-Min Lee. High-level Languages Assembly Languages Machine Languages.
RISC Concepts, MIPS ISA and the Mini–MIPS project
Choice for the rest of the semester New Plan –assembler and machine language –Operating systems Process scheduling Memory management File system Optimization.
Topics covered: ARM Instruction Set Architecture CSE 243: Introduction to Computer Architecture and Hardware/Software Interface.
8051 ASSEMBLY LANGUAGE PROGRAMMING
Data Transfer & Decisions I (1) Fall 2005 Lecture 3: MIPS Assembly language Decisions I.
Computer Architecture
ARM Core Architecture. Common ARM Cortex Core In the case of ARM-based microcontrollers a company named ARM Holdings designs the core and licenses it.
MIPS Instruction Set Advantages
CEG 320/520: Computer Organization and Assembly Language ProgrammingFlow Control 1 Flow Control.
Instruction Set Architecture
ITEC 352 Lecture 20 JVM Intro. Functions + Assembly Review Questions? Project due today Activation record –How is it used?
ITEC 352 Lecture 12 ISA(3). Review Buses Memory ALU Registers Process of compiling.
CS 147 June 13, 2001 Levels of Programming Languages Svetlana Velyutina.
ECE 265 – LECTURE 8 The M68HC11 Basic Instruction Set The remaining instructions 10/20/ ECE265.
Languages and the Machine Chapter 5 CS221. Topics The Compilation Process The Assembly Process Linking and Loading Macros We will skip –Case Study: Extensions.
ITEC 352 Lecture 14 ISA(6). Review Questions? Beginning / End Memory locations Variable / Memory syntax PSR Loops / Branches.
R3000/001 Assembly Programming using MIPS R3000 CPU R3000 CPU Chip Manufactured by IDT What is MIPS R3000 Processor? A 32-bit RISC CPU developed by MIPS.
Execution of an instruction
Lecture 4: MIPS Instruction Set
IFT 201: Unit 1 Lecture 1.3: Processor Architecture-3
MIPS coding. Review Shifting – Shift Left Logical (sll) – Shift Right Logical (srl) – Moves all of the bits to the left/right and fills in gap with 0’s.
Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Control Unit.
1 The Instruction Set Architecture September 27 th, 2007 By: Corbin Johnson CS 146.
ECE 447: Lecture 11 Introduction to Programming in Assembly Language.
Digital Computer Concept and Practice Copyright ©2012 by Jaejin Lee Control Unit.
SPARC Programming Model 24 “window” registers 8 global registers Control registers –Multiply step –PSR (status flags, etc.) –Trap Base register –Window.
ITEC 352 Lecture 16 ISA(7). Review Exam / Questions? Conditional codes, how important are they? How important are comments in assembly? What are the benefits.
CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.
MIPS Instruction Set Advantages
Control Unit Lecture 6.
Assembly Language Programming of 8085
Microprocessor T. Y. B. Sc..
ARM Registers Register – internal CPU hardware device that stores binary data; can be accessed much more rapidly than a location in RAM ARM has.
3.Instruction Set of 8085 Consists of 74 operation codes, e.g. MOV
Lecture 4: MIPS Instruction Set
RISC Concepts, MIPS ISA Logic Design Tutorial 8.
Conditional Branches What distinguishes a computer from a simple calculator is its ability to make decisions Decisions are made using the if statement,
Assembly Programming using MIPS R3000 CPU
Lecture 4: MIPS Instruction Set
CSC 3210 Computer Organization and Programming
ECE232: Hardware Organization and Design
COMS 361 Computer Organization
Assembly Programming using MIPS R3000 CPU
8051 ASSEMBLY LANGUAGE PROGRAMMING
MIPS Assembly.
MIPS instructions.
Presentation transcript:

Cosc 2150: Computer Organization ARC assembly code Simplified SPARC language 1

There are 32 32-bit registers. %r0 through %r31. Reserved registers: ARC Hardware There are 32 32-bit registers. %r0 through %r31. Reserved registers: %r0 is always 0. Storing anything in %r0 will be lost. %r14 is a stack pointer register also called %sp %r15 is link register (used for subroutine calls) 2

The ARCTools Simulator Window

There are two addition registers %pc, a 32-bit program counter register %psr, which is a processor status register Where arithmetic/logic flags are set. They are N,Z,V,C, where N is a negative flag Z is the zero flag V is the overflow flag C is the carry flag. The lowest 211 = 2048 addresses of the memory map are reserved for use by the operating system. 4

A Basic ARC assembly program .begin .org 2048 !Lowest space in memory a program can go main: !special label, for start of your code !Assembly instructions halt !end of assembly code var: value ! variable: value of the variable. .end 5

Arithmetic instructions All arithmetic and logic instructions have 3 opcode: instruction op1, op2, op3. Only op2 can be immediate load/ number otherwise, they will refer to a register. Any instructions that end in a cc, set condition codes (NZVC) addcc %r0, 1, %r1 (%r1 = 0 + 1) would set N=0, Z=0, V=0, and C=0 subcc %r0, 1, %r1 (%r1 = 0 – 1) would set N=1, Z=0, V=1, and C=0 Assuming %r1 = 1, subcc %r1, 1, %r1 (%r1 = %r1 –1), would set N=0, Z=1, V=0, and C=0 6

Data transfer instructions All have 2 opcode instructions. load: ld [x], %r1 !load the value of x into %r1 ld %r1+x, %r2 !load the value found by %r1 +x (offset) into %r2 store: st %r1, [x] !store the value of %r1 into x st %r2, %r1+x ! store the value of %r2 into the address %r1 +x 7

Branch instructions All but one branch instruction have a single opcode in the following format branch label ! branch conditionally or unconditionally to the label example: ba done !branch to the label done ! assembly code done: halt ! stop the program be, bcs, bcc, bneg, bvs, bvc, bne, bpos all use the NZVC condition flags to as the condition whether to branch or not. jmpl and call are used for subroutines, which will be covered later. 8

The ARCTools Edit Window

The ARCTools Edit Window • The Edit window with an asm file and the file dialog

Assembly The arc4 program after assembly, showing arc4.lst, the listing file.

Binary File The arc4 bin file, displayed after pressing the Show Binary File button.

Simulation The ARCTools simulator window after pressing Bin -> Sim.

Simulator note. You need a blank line at the end of the program or the program will not compile with normally a very strange error that makes no sense.

ARC example code (1) Example 1 main () { int a=15, b=5,c; c = a+ b; } .begin .org 2048 main: ! c = a +b ld [a], %r1 ld [b], %r2 addcc %r1, %r2, %r3 st %r3, [c] halt a: 15 b: 5 c: 0 .end 15

ARC Example code (2) Example 2 main() { int a =2, c=0; if (a == 2) { c =a*4; } else { c = a/2; } .begin .org 2048 main: ld [a], %r1 !if (a==2) subcc %r1, 2, %r0 bne else ! true c= a*4 sll %r1, 2, %r1 ba done ! false c = a/2 else: srl %r1, 1, %r1 done: st %r1, [c] halt a: 2 c: 0 .end

ARC code example (3) Example 3 main () { int a=15, b=5, c; if (a>=b) c = a - b; else c a + b; }   .begin .org 2048 main: ld [a], %r1 ld [b], %r2 !if (a>=b) subcc %r1, %r2, %r3 bneg false st %r3, [c] ba done false: add %r1, %r2, %r3 done: halt a: 15 b: 5 c: 0 .end 17

ARC code example (4) Example 4 main () { int x = 0; while (x <5) { x = x +1; } .begin .org 2048 main: ld [x], %r1 !while (x<5) top: subcc %r1, 5, %r0 bpos done !x = x+1 add %r1, 1, %r1 st %r1, [x] ba top done: halt x: 0 .end 18

ARC code example (4 modified) main () { int x = 0; while (x <=5) { x = x +1; } .begin .org 2048 main: ld [x], %r1 top: subcc %r1, 5, %r2 subcc %r2, 1, %r0 bpos done add %r1, 1, %r1 st %r1, [x] ba top done: halt x: 0 .end 19

What is the logic to figure out the following Helpful things to know What is the logic to figure out the following If (a>=b) or (a>=1) or any constant If (a>b) or (a> 1) If (a < b) or (1 < b) If (a <= b) or (1 <= b) If (a==1) or (a==b) Complex if statements If ( (a >10) && (b < 10) )

ARC code example (5) Example 5 int a=2, b=2, i=1; while (i < 5) { } Give it a try 21

ARC code example (5 cont.) .begin .org 2048 main: ld [i], %r1 top: subcc %r1, 5, %r0 bpos done ld [a], %r2 ld [b], %r3 add %r2, %r3, %r2 st %r2, [a] add %r1, 1, %r1 st %r1, [i] ba top done: halt a: 2 b: 2 i: 1 .end 22

Q A & 23