MOdel-based GENeration of Tests for Embedded Systems # FP7-ICT Embedded Systems Design WP3 Modelling & Testing Theory Modelling Examples Wolfgang Herzner, ARC

MOdel-based GENeration of Tests for Embedded Systems # FP7-ICT Embedded Systems Design Slide 2 MOGENTES Review, Brussels, 13 March 2009 WP3 / Modelling examples Modelling Languages  “User-level" modelling languages:  UML subset Class Diagrams State Diagrams OCL constraints  Simulink/Stateflow  Prover iLock  Modelling languages for test-case generation:  Action Systems semantics as presented before Consequences:  requires transformations  frees users from dealing with (unfamiliar) formal languages common to / accepted by domain experts

MOdel-based GENeration of Tests for Embedded Systems # FP7-ICT Embedded Systems Design Slide 3 MOGENTES Review, Brussels, 13 March 2009 WP3 / Modelling examples Modelling Example – Elektra (1)  Example for class diagrams (Papyrus 1.10)

MOdel-based GENeration of Tests for Embedded Systems # FP7-ICT Embedded Systems Design Slide 4 MOGENTES Review, Brussels, 13 March 2009 WP3 / Modelling examples Modelling Example – Elektra (2)  Examples for OCL-constraints (Papyrus 1.10) context TR_TrainRoute inv ValidGoal : /* selected goal signal must be projected as goal or start/goal signal */ self.oclIsInState(Selection) implies goal.oclIsTypeOf(MPS) implies goal.oclAsType(MPS).goal = true or goal.oclAsType(MPS).startgoal = true context TR_TrainRoute inv GoalElement : /* assure that front of goal signal actually points at first entry of trackelements or goal point is actually last entry of trackelements */ self.oclIsInState(Selection) implies if goal.oclIsTypeOf(MPS) then goal.oclAsType(MPS).front.owner = trackelements->last() else goal.oclAsType(TEP_).owner = trackelements->last() endif

MOdel-based GENeration of Tests for Embedded Systems # FP7-ICT Embedded Systems Design Slide 5 MOGENTES Review, Brussels, 13 March 2009 WP3 / Modelling examples Modelling Example – Relab Demonstrator (1)  Example for class diagrams (roclet)

MOdel-based GENeration of Tests for Embedded Systems # FP7-ICT Embedded Systems Design Slide 6 MOGENTES Review, Brussels, 13 March 2009 WP3 / Modelling examples Modelling Example – Relab Demonstrator (2) Example Requirements and Constraints: -- R PORT A and PORT B cannot be powered at the same time. context ECU_current_output inv: self.electromagnet_1_port_A = 0 or self.electromagnet_1_port_B = 0 -- R4.7. When the system is in the filtering status and a certain number of errors is detected that is greater than the constant K, the system must get into the STOP state. context ECU.invalidMessage() post: unvalid_data_counter > 100 and = ErrorState::FILTERING implies state = ErrorState::STOP

MOdel-based GENeration of Tests for Embedded Systems # FP7-ICT Embedded Systems Design Slide 7 MOGENTES Review, Brussels, 13 March 2009 WP3 / Modelling examples Modelling Examples – Next Steps  Completion of models  state diagrams  e.g. for ELEKTRA trainroutes  Specification of mapping to Action Systems semantics