Implementation of Phase Locked Loop (PLL) by using IC 565 and IC555 Clock Generator with Variable Frequency

Circuit Diagram

PINOUT of IC555

Circuit Description In the 555 Oscillator circuit below, pin 2 and pin 6 are connected together allowing the circuit to re-trigger itself on each and every cycle allowing it to operate as a free running oscillator. During each cycle capacitor, C charges up through both timing resistors, R1 and R2 but discharges itself only through resistor, R2 as the other side of R2 is connected to the discharge terminal, pin 7.

Circuit Description Then the capacitor charges up to 2/3Vcc (the upper comparator limit) which is determined by the 0.693(R1+R2)*C combination and discharges itself down to 1/3Vcc (the lower comparator limit)determined by the 0.693(R2*C) combination. This results in an output waveform whose voltage level is approximately equal to Vcc-1.5V and whose output “ON” and “OFF” time periods are determined by the capacitor and resistors combinations.

OUTPUT OF IC555

Implementation of Phase Locked Loop (PLL) A Phase Lock Loop (PLL) is an electronic circuit, which locks the phase of the input signal with that of the output by keeping them synchronized. It achieves this through a closed loop feedback mechanism that compares the input signal with the output and makes the necessary corrections so that the phase remains synchronous.

BLOCK DIAGRAM

BLOCK DIAGRAM DESCRIPTION PLL consist of Phase detector Low-pass filter Error amplifier Voltage Controlled Oscillator (VCO)

BLOCK DIAGRAM DESCRIPTION The phase detector compares the input frequency fi with the feedback frequency fo and generates an output signal which is a function of the difference between the phases of the two input signals. The output signal of the phase detector is a dc voltage.

BLOCK DIAGRAM DESCRIPTION The output of phase detector is applied to low-pass filter to remove high frequency noise from the dc voltage. The output of low pass filter without high frequency noise is often referred to as error voltage or control voltage for VCO.

BLOCK DIAGRAM DESCRIPTION When control voltage is zero, VCO is in free running mode and its output frequency is called as center frequency fo. The non-zero control voltage results in a shift in the VCO frequency from its free-running frequency, fo to a frequency f, given by f = fo + Kv .Vc Where, Kv is the voltage to frequency transfer coefficient of the VCO and Vc is the control voltage given to VCO.

Evaluation Parameters from PLL

CIRCUIT DIAGRAM

PINOUT OF IC565

Free running state of PLL (not in locking state)

Locking state of PLL

CONCLUSION By varying the frequency of 555 timer, one van able to find out the lock range of PLL. For the center frequency of 7.5 KHz, the locking range is found out from 4.5 KHz to 10 KHz.