CIS 6930: Chip Multiprocessor: GPU Architecture and Programming Fall 2010 Jih-Kwon Peir Computer Information Science Engineering University of Florida

Chapter 2 – History of GPU Computing Fixed-Function graphics pipeline Early era, early 1980 – late 1990 Programmable graphics unit Nvidia GeForce 3, introduced 2001 achieve shader programmability DirectX 8, OpenGL Unified Graphics and Computing Processors Nvidia GeForce 8800, introduced 2006 provides general- purpose GPUs

Fixed-Function Graphics Pipeline – Early Era Host CPU Host Interface GPU Vertex Control Vertex Cache Fixed-Function Graphics Pipeline – Early Era VS/T&L Triangle Setup Raster Frame Buffer Memory Texture Cache Shader ROP FBI

Texture Mapping Example Texture mapping example: painting a world map texture image onto a globe object. - At Shader stage

Anti-Aliasing Example – Raster Operation Stage Triangle Geometry Aliased Anti-Aliased

Programmable Vertex and Pixel Processors – Intermediate Step 3D Application or Game 3D API Commands CPU 3D API: OpenGL or Direct3D CPU – GPU Boundary GPU Command & Data Stream GPU Assembled Polygons, Lines, and Points Pixel Location Stream Vertex Index Stream Pixel Updates GPU Front End Primitive Assembly Rasterization & Interpolation Raster Operations Framebuffer Pre-transformed Vertices Rasterized Pre-transformed Fragments Transformed Vertices Transformed Fragments Programmable Vertex Processor Programmable Fragment (pixel) Processor An example of separate vertex processor and fragment processor in a programmable graphics pipeline

Unified Graphics Pipeline – TODAY! FB SP L1 TF Thread Processor Vtx Thread Issue Setup / Rstr / ZCull Geom Thread Issue Pixel Thread Issue Data Assembler Host

G80 CUDA mode – A Device Example Processors execute computing threads New operating mode/HW interface for computing Load/store Global Memory Thread Execution Manager Input Assembler Host Texture Parallel Data Cache