Preliminary design of the behavior level model of the chip Wei Wei 2018-6-25

Preliminary design of the behavior model Main purpose: to define the architecture of the chip and readout scheme Pixel array: Simplified pixel analog, main func: injection charge -> hit Pixel digital: hit generation and priority + address encoder Periphery: Column logic: priority acknowledgement + time stamp + column FIFO Chip level: chip level priority + trigger logic + chip FIFO Readout

Proposed architecture (for discussion) L1 FIFO In column level, to de-randomize the injecting charge L2 FIFO Chip level, to match the in/out data rate between the core and interface Trigger logic Make the data rate in a reasonable range

Pixel cell - analog Pixel analog: Estimation : Limit: Mainly to generate the hit, Others simplified Inj current + integration cap + follower + discriminator Input not randomly, to simply the array level simulation Discrimination: using a fixed global vth, not the real case No global vth will be provided Hit valid: by static set of the calibration enable, not the real case Maybe by slow control config. Estimation : Input current/hit: 160nA~2ns triangular current -> epi layer 12um, 80e-/um -> 1000e Cd: 2fF, can be modified if SNR will be evaluated Limit: No noise is added so far

Pixel cell – digital Has to work with the column controller Logic – all by Verilog Two functions: HIT generation and reset Priority arbitrary & Pixel readout One example of the gate level implement More or less FE-I3 like, but simplified Priority mask and arbitrary by the busy-bus (fast-or) Request for 2 latches One to latch the HIT One to latch the priority token Has to work with the column controller Address encoder: Not easy by Verilog code, implemented by enumeration rom; Suppose a 32*32 array Special layout in the real case

Column level logic Time stamp Priority Receive the busy signal, Generation read ack. when busy is lasting Precondition: the same column will be hit again in a short time Otherwise a freeze latch should be added Col. average hit period: 8.3us; cluster size: 3 pixels; clk 40MHz A freeze latch can actually be found in FE-I3 Suppose the data can be readout soon, and no new hit arrive in the same column Addr encoder Time stamp counter Priority Controller Time stamp regs RAM Controller Dual port RAM core Loop FIFO Time stamp Latching the time stamp @ the rising edge of busy Meaning all the simultaneously hit will have the same stamp Note: Time stamp nor clk is fanned out to pixels, only busy & read ack. propagate column-ly

Column FIFO Using a memory compiler by ARM to generate the Verilog code of a dual-port RAM Not the final case, can use any vender IP However, the readout & data related controller logic has to be based on the RAM time sequence A FIFO controller was implemented, and the dual-port RAM was packaged as a Loop FIFO 24 bits/hit will be saved: 9 bits addr code + 8 bits time stamp 24bits * 64 words RAM was supposed for every column Maybe not the final case

Column level simulation Fast or Column Read 1 Time stamp Latched TS 2 Pixel address Data restored into RAM 3 Data _WR of RAM Pixel 08/15/23 was valid for charge injection, and was hit at the same time Can be readout sequentially by the control of priority

Chip level logic 32-pixel column Tri-state data bus Pixel array 32*32 Chip level priority arbitration req-ack Column address encoder Chip level priority & Trigger logic Pixel array 32*32 Serializer missing Chip Loop FIFO

Chip level logic Chip level priority Trigger logic: similar as the column level Readout by the chip readout Controller Trigger logic: Compatible with triggerless readout Any hit will be readout under the priority arbitration First buffered in the Chip level FIFO, then serializer (not implemented) Trigger mode (preliminary): Readout Controller is suspended till trigger comes Time stamp of the trigger is latched the time stamp of the true event is calculated, by subtracting the length of trigger latency (can be configured by the slow control) Data readout begins, the recorded time stamp of the hits compared with the time stamp of the true event (within estimated error, can be configured by the slow control) When matched, will be saved into the chip level FIFO, then serializer

Chip level simulation- triggerless Stored data into chip FIFO Data bus Internal read in column 15 Internal read in column 06 Column address bus Column 06/15 & pixel 08/15 in each column is valid for charge injection (4 simultaneously hit pixels ) Simulation shows: Row & column address correctly encoded Column data were readout by priority arbitration In each column, the stored data were readout in a first-in-first-out style Data bus can be tri-statedly loaded, while the final data that were stored into the chip FIFO is clear

Chip level simulation- trigger mode(preliminary) True event time stamp Trigger time stamp Stored data into chip FIFO Trigger coincidence flag Event read bus Tri-state Data bus External trigger Column 06/15 & pixel 08/15 in each column is valid for charge injection (4 simultaneously hit pixels ), with 120ns injection period, first injection@700ns Trigger comes at 4.9us, suppose trigger latency 3us, meaning the true event was at 1.9us (time stamp 4b) Simulation shows: Trigger coincidence flag only valid during the event time stamp = 4b Only the matched data were stored into the chip FIFO, other data streamed away

Know bugs and designs left Trigger logic not fully done Should set a threshold, that the events later than the true event will stop the readout of current column, and wait for the next trigger Otherwise the next true event might be dropped, if the hit rate is high Power consumption not optimized In the current architecture, all the hit data will be running on the data bus that is chip level, 32-bit wide, a hot bus Readout & transfer first, then coincidence and buffered, not good Should move the trigger logic into the column level Coincidence first, then readout, power saving Data output interface not implemented Serializer Slow control not implemented Not important in the behavior level

Manual of using the library Top schematic for simulation Sim_array Open the config view, simulator->spectreVerilog Comments: Most of the library were based on pure Verilog, so no problem of NDA Only one IP: the RAM is from ARM (free of charge though) Please DO NOT propagate, THANKS

Preliminary consideration of the schedule From MOST2 project 05/2018 ~ 04/2019 the first MPW to be tapeout