Programmable Logic Controllers (PLCs) Software Timers ACOE347 Software Timers

Software Timer Instructions Timer Instructions are output instructions used to time intervals for which their rung conditions are true (TON), or false (TOF). These are software timers. Their resolution and accuracy depends on a tick timer maintained by the microprocessor. (Typical values are 1 sec, or 0.1 sec.) Each timer instruction has two values (integers) associated with it: Accumulated Value (ACC): This is the current number of ticks (time-base intervals) that have been counted from the moment that the timer has been energized. Preset Value (PR): This is a predetermined value set by the programmer. When the accumulated value is equal to, or greater than the preset value, a status bit is set. This bit can be used to control an output device. Each timer is associated with two status bits: Timer Enable Bit (EN): This bit is set when the rung condition to the left of the timer instruction are true. When this bit is set, the accumulated value is incremented on each time-base interval, until it reaches the preset value. Done Bit (DN): This bit is set when the accumulated value is equal to the preset value. It is reset when the rung condition becomes false. ACOE347 Software Timers

The Reset (RES) Instruction The RES instruction resets timing and counting instructions. When the RES instruction is enabled it resets the following: Counters: Accumulated value Counter Done Bit Counter Enabled Bit Timers: Timer Done Bit Timer Enable Bit Reset ladder diagram example: ACOE347 Software Timers

Timer On-Delay (TON) Instruction The TON instruction begins count timebase pulses when its input rung conditions are true. The accumulated value is reset when the input rung conditions become false, or when the ‘Res’ signal is activated. The DN bit is set when the preset value is reached Typical timing diagram (Assume that Preset = 05) ACOE347 Software Timers

Self-Restart Timer On-Delay To restart a timer automatically, whenever the preset value is reached, connect to the Timer enable line the inverted Timer Done bit. Initially the Done bit is cleared, and the timer enable bit is set (since the done bit is inverted) Thus the time will start counting. When the preset value is reached, the Done bit is set Thus the Enable bit will be cleared and the timer will reset After the timer is reset, the Done bit will be cleared and the enable bit will be set and the timer will start counting again Typical timing diagram (Assume that Preset = 05) ACOE347 Software Timers

Timer On-Delay with Hold-On Contact The timer runs for as long as its Timer Enable input is activated. If the input condition is activated for a time period shorter than the Preset value, the timer will reset and stop counting before the predefined period. To keep the timer running, even if the input condition becomes false, we can connect the Timer Enable bit in parallel with the input device that starts the timer. This connection is called the Hold-On contact. Typical timing diagram (Assume that Preset = 05) Hold-On Contact ACOE347 Software Timers

Timer On-Delay with Hold-On Contact and Self Reset To reset a timer automatically, whenever the preset value is reached, connect to the Timer enable line the inverted Timer Done bit. The timer will start counting after the input switch is momentarily pressed Note that if the Time Enable input is reset the Timer Done bit will be set instantly and then reset. To maintain the Timer Done condition, we can connect it to a Latch Output flag. Typical timing diagram (Assume that Preset = 05) ACOE347 Software Timers

Latched-On-Delay Timer (LOD) Instruction The LOD instruction begins count timebase pulses when its input rung condition becomes true, and continues counting even if the input rung becomes false. The accumulated value is reset whenever the ‘RES’ bit is set. This instruction is not supported by PSIM Typical timing diagram (Assume that Preset = 05) ACOE347 Software Timers

Retentive Timer (RTO) Instruction The RTO instruction begins count timebase pulses when its input rung conditions are true. The accumulated value is retained when the input rung conditions become false, and continues counting after the input rung conditions become true. Timer ladder diagram example: Typical timing diagram (Assume that Preset = 07) ACOE347 Software Timers

Programmable Logic Controllers (PLCs) Ladder Implementation of Clocked Circuits Edge Detection Clock Generation Monostable Circuits (One Shots) ACOE347 Software Timers

PLC Scan Cycle Clock generators and monostable circuits rely one edge detection. Most PLCs programming environments support edge detection input instructions. If edge detection input instructions are not supported, these can be implemented using the 1-scan cycle delay between input changes and output updates. When an output is used as input instruction, most PLCs use the corresponding value from the Output Memory Image. This is essential in achieving the parallel execution of the rungs. Scan Cycle N Scan Cycle N-1 When an output is used as input instruction, some PLCs and Simulators use the values calculated during the current scan cycle, thus the behaviour of the PLC might change according to the order of appearance of the rungs in the ladder diagram. ACOE347 Software Timers

Positive Edge Detection ACOE347 Software Timers

Clock Generation (f = scan frequency) ACOE347 Software Timers

Clock generator with specific frequency ACOE347 Software Timers

Monostables – One Shots A monostable has only one stable output state. The other output state can only be maintained temporarily Monostable, also called one-shots, come in two basic varieties: retriggerable and nonretriggerable ACOE347 Software Timers

Monostable Ladder diagram implementation ACOE347 Software Timers

Non Retriggerable One Shot Positive edge detection ACOE347 Software Timers

Retriggerable One Shot Positive edge detection ACOE347 Software Timers