SCMP 368.00 Software Development Spring 2018 James Skon Make Files with C++ SCMP 368.00 Software Development Spring 2018 James Skon

What is Make? A utility which maintains up-to-date versions of programs. Based on rules defined in a "makefile" it will rebuild executables by determining which modules need to be recompiled whenever you make changes to the original source code.

Make Dependancies A "makefile" is a list of rules and dependencies with corresponding commands to create "targets" using the rules and dependencies. We will be using a makefile to manage a list of files that "make" or build a C++ programs.

Make Dependancies A C++ program can be (and usually is) built with several source code files and several header files. Source code files are usually a collection of .cpp files and .h header files.

Make Dependancies When a program has a large number of source files, the files typically depend on one another in complex ways. Whenever changes are made to one file that other files depend on, all dependent files will need to be recompiled.

Make Dependancies Determining exactly which files need to be updated can be difficult and time-consuming task. The alternative, recompiling all source files regardless of whether it is necessary, wastes both cpu and elapsed time.

Make The make utility permits the definition of program dependencies by specifying the appropriate rules

Using Make when run, make reads a dependency information is read from a file named makefile (or Makefile) in the current working directory. By using the -f flag, you can specify that another filename holds this information. % make % make -f makeprog2

Using Make A simple makefile has the following form: target-file: prerequisite-file-list (tab) construction-commands target-file is the name of the a file prerequisite-file-list is the files that target-file depends on. construction-commands is a list of commands to build the target file. must start with a TAB

An Example Lets say we have 3 .cpp files and 2 .h files that make up our program. They are: main1.cpp mylib.cpp mylib.h openfile.cpp openfile.h Want to create an executable named my_lab

Label and dependancies Example Makefile TAB Comment # Makefile for my_lab my_lab: main1.o mylib.o openfile.o g++ -o my_lab main1.o mylib.o openfile.o main1.o: main1.cpp openfile.h mylib.h g++ -c main1.cpp mylib.o: mylib.cpp mylib.h g++ -c mylib.cpp openfile.o: openfile.cpp openfile.h g++ -c openfile.cpp clean: rm *.o lab1.out Label and dependancies Actions

Make Makefiles can include comments, delimited by hash marks (#). A backslash (\) can be used at the end of a line to continue a command onto the next physical line. If needed, multiple shell commands can be issued to build a specified target file. Each construction command should be placed on its own line, indented by tabs.

How Make Works To keep a collection of subprograms up to date make compares the modification time of the target file with the modification times of the prerequisite files. Any prerequisite file that has a more recent modification time than its target file forces the target file to be recreated.

How Make Works By default, the first target file appearing in the makefile is the one that is built. Other targets are only checked if they are a prerequisite for the initial target. Other than the fact that the first target in the makefile is the default, the order of the targets does not matter. The make utility will build them in the order required.

Verifying Makefile Formats You can test makefiles by using the -n option. This option causes the make utility to display, but not execute, all the commands it would normally execute to build the program.

A Simple Makefile Example Main program source is in abc.cpp, Subroutines in a.cpp, b.cpp and c.cpp. All use abc.h Thus, the executable program will depend on all four of these files.

A Simple Makefile Example /* abc.cpp */ main() { a(); b(); c(); } /* a.cpp */ #include <stdio.h> a() printf("A\n"); /* b.cpp */ #include <stdio.h> b() { printf("B\n"); } /* c.cpp */ c() printf("C\n");

A Simple Makefile Example # makefile : makes the ABC program abc : a.o b.o c.o abc.o g++ -o abc abc.o a.o b.o c.o abc.o : abc.cpp g++ -O -c abc.cpp a.o : a.cpp, abc.h g++ -O -c a.cpp b.o : b.cpp , abc.h g++ -O -c b.cpp c.o : c.cpp , abc.h g++ -O -c c.cpp

Internal Make Rules You can rely on implied dependencies and construction commands (or internal rules) to simplify your makefile. A list of internal rules allows the make utility to understand how to create a file with one suffix from a file with another suffix.

Internal Make Rules Example Consider the following programs /* A sample program to illustrate the MAKE utility */ #include <stdio.h> main() { printf("Working\n"); compute_sales_figures(); printf(".\n"); pay_employees(); printf("Done\n"); }

Internal Make Rules Example pay_employees() { int i, k; for (i=1; i<100; ++i) k = i + 1; }

Internal Make Rules Example /* A sample program to illustrate the MAKE utility */ #include <stdio.h> compute_sales_figures() { int i, k; for (i=1; i<100; ++i) k = i + 1; }

Internal Make Rules Example Now consider the following makefile: # makefile : makes the payroll program # for the make tutorial # Default construction commands will # build the object files: # salary.o and sales.o payroll : salary.o sales.o g++ salary.o sales.o -o payroll

Internal Make Rules Example Notice that there is only one dependency line: salary.o sales.o Neither of these object files are listed as targets in the makefile make will search for source code in the working directory from which to build the object file based on the default construction commands.

Default construction commands By default, if an object file without a target is created as follows: g++ -O -c file.cpp Thus, in the case of the above example, we get: g++ -O -c salary.cpp g++ -O -c sales.cpp

Default construction commands If the default behavior is not what you want, you must explicitly give the instructions in the makefile.

Make Macros The make utility supports a sophisticated macro ability. In a manner similar to UNIX shell variables, macros can be used to substitute one set of character sequences for another.

Make Macros macroname = replacestring You can define macros in your makefile with an entry of the following form: macroname = replacestring The replacestring can consist of all characters on a single line before a comment character (#).

Make Macros Macros can be continued onto additional successive lines by using line continuations (\). Make will replace each of the characters $(macroname) in the makefile with the given replacestring.

Make Macros example # payroll2.make: another makefile for the payroll program # used in thr make tutorial. CFLAGS = -g -O # compiler options payroll : salary.o sales.o g++ -o payroll salary.o sales.o salary.o : salary.cpp g++ -c $(CFLAGS) salary.cpp sales.o : sales.cpp g++ -c $(CFLAGS) sales.cpp

Make Macros example By putting the compiler flags in a macro, you can easily change them in just one place rather than on every individual compile command.