Computer System Design Lecture 9

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Presentation transcript:

241-440 Computer System Design Lecture 9 Wannarat Suntiamorntut 241-440 @ W.S.

Memory Technology 241-440 @ W.S.

Technology Trend Capacity Speed Logic : 2x in 3 years 2x in 3 years DRAM : 4x in 3 years 2x in 10 years Disk : 4x in 3 years 2x in 10 years 241-440 @ W.S.

Processor-DRAM memory Gap 241-440 @ W.S.

Expanded of Memory System 241-440 @ W.S.

Hierarchy of Modern computer 241-440 @ W.S.

How hierarchy manage? Registers <--> Memory by compiler Cache <--> Memory by Hardware Memory <--> Disks by Hardware/OS, programmer (files) 241-440 @ W.S.

Logic Diagram of a Typical SRAM 241-440 @ W.S.

Typical of SRAM Timing 241-440 @ W.S.

Classical DRAM Organization 241-440 @ W.S.

Logic Diagram of a Typical DRAM 241-440 @ W.S.

Art of Memory Design 241-440 @ W.S.

1 KB Direct Mapped Cache with 32 B Blocks 241-440 @ W.S.

Example : Fully Associative 241-440 @ W.S.

A Two-way Set Associative Cache 241-440 @ W.S.

Disadvantage of Set Associative Cache 241-440 @ W.S.

How do you Design Cache? 241-440 @ W.S.

1 KB Direct mapped Cache, 32B blocks 241-440 @ W.S.

Improvement of Cache Reduce Miss rate Reduce Miss penalty Reduce time to hit in cache 241-440 @ W.S.

Where can a block be placed in the upper level? 241-440 @ W.S.

Example 241-440 @ W.S.

Next on Lecture 10 241-440 @ W.S.