11.1 Interrupt Mechanism, Type, and Priority Interrupts provide a mechanism for quickly changing program environment. Transfer of program control is initiated by the occurrence of either an event internal to the microprocessor or an event in its external hardware.

11.1 Interrupt Mechanism, Type, and Priority When an interrupt signal occurs in external hardware indicating that an external device, such as a printer, requires service, the MPU must suspend what it is doing in the main part of the program and pass control to a special routine (interrupt-service routine) that performs the function required by the device. In the case of our example of a printer, the routine is usually called the printer driver, which is the piece of software when executed drives the printer output interface.

Interrupt mechanism The 8088 and 8086 microcomputers are capable of implementing any combination of up to 256 interrupts. As Fig. 11-2, they are divided into five groups: external hardware interrupts, nonmaskable interrupt, software interrupts, internal interrupts, and reset.

Figure 11.2 Types of interrupts and their priority

Interrupt mechanism The user defines the function of the external hardware, software, and nonmaskable interrupt. For instant, hardware interrupt are often assigned to devices such as the keyboard, printer, and timers. On the other hand, the function of the internal interrupts and reset are not user defined. They perform dedicated system functions.

Interrupt mechanism Hardware, software, and internal interrupts are serviced on a priority basis. Priority is achieved in two ways. First, the interrupt-processing sequence implemented in the 8088/8086 tests the occurrence of the various groups based on the hierarchy shown in Fig. 11-2. Thus, we see that internal interrupts are the highest-priority group, and the external hardware interrupts are the lowest-priority group.

Interrupt mechanism Second, each of the interrupts is given a different priority level by assigning it a type number. Type 0 identifies the highest-priority interrupt, and type 255 identifies the lowest-priority interrupt. Actually, a few of the type numbers are not available for use with software or hardware interrupts. This is because they are reserved for special interrupt functions of the 8088/8086, such as internal interrupts.

Interrupt mechanism For instant, within the internal interrupt group, the interrupt known as divide error is assigned to type number 0. Therefore, it has the highest priority of the internal interrupts. Another internal interrupt, called overflow, is assigned the type number 4, Overflow is lowest-priority internal interrupt.

Interrupt mechanism The importance of priority lies in the fact that, if an interrupt-service routine has been initiated to perform a function assigned to s specific priority level, only devices with higher priority are allowed are allowed to interrupt the active service routine. Lower-priority devices will have to wait until the current routine is completed before their for service can be acknowledged.

Interrupt mechanism For hardware interrupts, this priority scheme is implemented in external hardware. For this reason, the user normally assigns tasks that must not be interrupted frequently to higher-priority levels and those can not be interrupted to lower-priority levels.

Interrupt mechanism An example of a high-priority service routine that should not be interrupted is that for power failure. Once initiated, this routine should be quickly run to completion to assure that the microcomputer goes through an orderly power-down.

Interrupt mechanism A keyboard should also be assigned to a high-priority interrupt. This will assure that the keyboard buffer does not get full and lock out additional entries. On the other hand, device such as the floppy disk or hard disk controller are typically assigned to a lower priority level.

11.2 Interrupt vector table An interrupt vector table is used to link the interrupt type numbers to the location of their service routine in the program-storage memory. Fig. 11-2 contains 256 address pointers (vectors), which are identified as vector 0 through vector 255. That is, one pointer corresponds to each of the interrupt types 0 through 255. These pointers identify the starting location of their service routines in program memory. The contents of this table may be either held as firmware in EPROMs or loaded into RAM as part of the system initialization routine.

11.2 Interrupt vector table Fig. 11-3 starts at address 0000016 and end at 003FE16. This represent the first 1Kbytes of memory. Each of the 256 pointers requires two words (4 bytes) of memory and is always stored at an even-address boundary. The higher-addressed word of the two-word vector is called the base address. IT identifies the program memory segment in which the service routine resides.

Figure 11.3

11.2 Interrupt vector table For example, the offset and base address for type number 255, IP255 and CS255, are stored at word addresses 003FC16 and 003FE16, respectively. When loaded into the MPU, it points to the instruction at CS255:IP255

11.2 Interrupt vector table Looking more closely at the table in Fig. 11-3, we find that the first 31 pointers either have dedicated functions or are reserved. For instance, pointers 1, 2, 3, and 4 are used by the 8088’s and 8086’s internal interrupts: divide error, single step, breakpoint, and overflow. Pointer 2 is used to identify the starting location of the nonmaskable interrupt’s service routine. The next 27 pointers, 5 through 31, represent a reserved portion of the pointer table and should not be used.

11.2 Interrupt vector table The remainder of the table , the 224 pointers in the address range 0008016 through 003FF16, is available to the user for storage of software or hardware interrupt vectors. These pointers correspond to type number 32 through 255. In the case of external hardware interrupts, each type number (priority level) is associated with an interrupt input in the external interrupt interface circuitry.

Ex 11.1

11-3 Interrupt instructions The first interrupt instructions, STI and CLI, permit manipulation interrupt flag through software. STI stands for set interrupt enable flag. Execution of this instruction enables the external interrupt request (INTR) input for operation-that is, it sets interrupt flag (IF). On the other hand, execution of CLI (clear interrupt enable flag) disables the external interrupt input by resetting IF.

11.3 Interrupt Instructions Figure 11.4

11.External Hardware-Interrupt Interface Siganl Figure 11.5

Figure 11.6

Figure 11.7

Figure 11.8