Compiler Construction CS 606 Sohail Aslam Lecture 3 compiler: intro

Syntax Tree x+2-y goal expr term op – <id,y> <id,x> + <number, 2> x+2-y

Abstract Syntax Trees The parse tree contains a lot of unneeded information. Compilers often use an abstract syntax tree (AST).

Abstract Syntax Trees This is much more concise – + <id,y> <id,x> <number,2> This is much more concise

Abstract Syntax Trees – + <id,y> <id,x> <number,2> AST summarizes grammatical structure without the details of derivation

Abstract Syntax Trees – + <id,y> <id,x> <number,2> ASTs are one kind of intermediate representation (IR)

The Back End Instruction selection IR machine code errors Register allocation scheduling

The Back End Translate IR into target machine code. Choose machine (assembly) instructions to implement each IR operation

The Back End Ensure conformance with system interfaces Decide which values to keep in registers

The Back End Instruction Selection: Produce fast, compact code. IR machine code errors Register allocation scheduling Instruction Selection: Produce fast, compact code.

The Back End Instruction Selection: IR machine code errors Register allocation scheduling Instruction Selection: Take advantage of target features such as addressing modes.

The Back End Instruction Selection: IR machine code errors Register allocation scheduling Instruction Selection: Usually viewed as a pattern matching problem – dynamic programming.

The Back End Instruction Selection: IR machine code errors Register allocation scheduling Instruction Selection: Spurred by PDP-11 to VAX-11 - CISC.

The Back End Instruction Selection: IR machine code errors Register allocation scheduling Instruction Selection: RISC architecture simplified this problem.

The Back End Register Allocation: IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Have each value in a register when it is used.

The Back End Register Allocation: IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Manage a limited set of resources – register file.

The Back End Register Allocation: IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Can change instruction choices and insert LOADs and STOREs.

The Back End Register Allocation: IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Optimal register allocation is NP-Complete.

The Back End Instruction Scheduling: IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Instruction Scheduling: Avoid hardware stalls and interlocks.

The Back End Instruction Scheduling: IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Instruction Scheduling: Use all functional units productively.

The Back End Instruction Scheduling: IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Instruction Scheduling: Optimal scheduling is NP-Complete in nearly all cases.