Optimal Bus Sequencing for Escape Routing in Dense PCBs H.Kong, T.Yan, M.D.F.Wong and M.M.Ozdal Department of ECE, University of Illinois at U-C ICCAD.

Slides:



Advertisements
Similar presentations
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks Tan Yan*, Shuting Li Yasuhiro Takashima, Hiroshi Murata The University.
Advertisements

Cognitive Radio Communications and Networks: Principles and Practice By A. M. Wyglinski, M. Nekovee, Y. T. Hou (Elsevier, December 2009) 1 Chapter 12 Cross-Layer.
THERMAL-AWARE BUS-DRIVEN FLOORPLANNING PO-HSUN WU & TSUNG-YI HO Department of Computer Science and Information Engineering, National Cheng Kung University.
Constraint Driven I/O Planning and Placement for Chip-package Co-design Jinjun Xiong, Yiuchung Wong, Egino Sarto, Lei He University of California, Los.
Memory Aid Help.  b 2 = c 2 - a 2  a 2 = c 2 - b 2  “c” must be the hypotenuse.  In a right triangle that has 30 o and 60 o angles, the longest.
Dynamic Programming.
A Routing Technique for Structured Designs which Exploits Regularity Sabyasachi Das Intel Corporation Sunil P. Khatri Univ. of Colorado, Boulder.
1.1 Data Structure and Algorithm Lecture 6 Greedy Algorithm Topics Reference: Introduction to Algorithm by Cormen Chapter 17: Greedy Algorithm.
Greedy Algorithms Greed is good. (Some of the time)
Wen-Hao Liu1, Yih-Lang Li, and Cheng-Kok Koh Department of Computer Science, National Chiao-Tung University School of Electrical and Computer Engineering,
A Size Scaling Approach for Mixed-size Placement Kalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan School of Electrical and Computer Engineering.
Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Incidences and Many Faces via cuttings Sivanne Goldfarb
An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois.
MCFRoute: A Detailed Router Based on Multi- Commodity Flow Method Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li.
An efficient algorithm for optimizing whole genome alignment with noise P. Wong, T. Lam, N. Lu, H. Ting, and S. Yiu Department of Computer Science, University.
Penn ESE535 Spring DeHon 1 ESE535: Electronic Design Automation Day 19: April 9, 2008 Routing 1.
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
Metal Layer Planning for Silicon Interposers with Consideration of Routability and Manufacturing Cost W. Liu, T. Chien and T. Wang Department of CS, NTHU,
Constrained Pattern Assignment for Standard Cell Based Triple Patterning Lithography H. Tian, Y. Du, H. Zhang, Z. Xiao, M. D.F. Wong Department of ECE,
Multi-Layer Channel Routing Complexity and Algorithm Rajat K. Pal.
7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.
Chip Planning 1. Introduction Chip Planning:  Deals with large modules with −known areas −fixed/changeable shapes −(possibly fixed locations for some.
General Routing Overview and Channel Routing
MGR: Multi-Level Global Router Yue Xu and Chris Chu Department of Electrical and Computer Engineering Iowa State University ICCAD
9/4/ VLSI Physical Design Automation Prof. David Pan Office: ACES Detailed Routing (I)
Authors: Jia-Wei Fang,Chin-Hsiung Hsu,and Yao-Wen Chang DAC 2007 speaker: sheng yi An Integer Linear Programming Based Routing Algorithm for Flip-Chip.
Escape Routing For Dense Pin Clusters In Integrated Circuits Mustafa Ozdal, Design Automation Conference, 2007 Mustafa Ozdal, IEEE Trans. on CAD, 2009.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
1 Global Routing Method for 2-Layer Ball Grid Array Packages Yukiko Kubo*, Atsushi Takahashi** * The University of Kitakyushu ** Tokyo Institute of Technology.
Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-Path Steiner Graph Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, and Shih-Hung Weng UC San.
Archer: A History-Driven Global Routing Algorithm Mustafa Ozdal Intel Corporation Martin D. F. Wong Univ. of Illinois at Urbana-Champaign Mustafa Ozdal.
BSG-Route: A Length-Matching Router for General Topology T. Yan and M. D. F. Wong University of Illinois at Urbana-Champaign ICCAD 2008.
Efficient Multi-Layer Obstacle- Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu,Meng-Xiang Li, Yao-Wen Chang.
1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 8 Lecture 8 Network Flow Based Modeling Mustafa Ozdal Computer Engineering Department,
Thermal-aware Steiner Routing for 3D Stacked ICs M. Pathak and S.K. Lim Georgia Institute of Technology ICCAD 07.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
The Fast Optimal Voltage Partitioning Algorithm For Peak Power Density Minimization Jia Wang, Shiyan Hu Department of Electrical and Computer Engineering.
AUTOMATIC BUS PLANNER FOR DENSE PCBS Hui Kong, Tan Yan and Martin D.F. Wong Department of Electrical and Computer Engineering, University of Illinois at.
Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen Chang
ARCHER:A HISTORY-DRIVEN GLOBAL ROUTING ALGORITHM Muhammet Mustafa Ozdal, Martin D. F. Wong ICCAD ’ 07.
B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing L. Luo, T. Yan, Q. Ma, M. D.F. Wong and T. Shibuya Department of Electrical.
ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips Chiung-Yu Lin and Yao-Wen Chang Department of EE, NTU DAC 2009.
Exact routing for digital microfluidic biochips with temporary blockages OLIVER KESZOCZE ROBERT WILLE ROLF DRECHSLER ICCAD’14.
A Negotiated Congestion based Router for Simultaneous Escape Routing Q.Ma, T.Yan and Martin D.F. Wong Department of Electrical and Computer Engineering.
Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng NTU &Synopsys An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs.
Escape Routing of Mixed-Pattern Signals Based on Staggered-Pin- Array PCBs K. Wang, H. Wang and S. Dong Department of Computer Science & Technology, Tsinghua.
On Routing Fixed Escaped Boundary Pins for High Speed Boards T. Tsai, R. Lee, C. Chin and Y. Kajitani Global UniChip Corp. Hsinchu, Taiwan DATE 2011.
CALTECH CS137 Winter DeHon CS137: Electronic Design Automation Day 13: February 20, 2002 Routing 1.
ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National.
Parallel and Distributed Simulation Time Parallel Simulation.
Maze Routing Algorithms with Exact Matching Constraints for Analog and Mixed Signal Designs M. M. Ozdal and R. F. Hentschke Intel Corporation ICCAD 2012.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
1 CS612 Algorithms for Electronic Design Automation CS 612 – Lecture 8 Lecture 8 Network Flow Based Modeling Mustafa Ozdal Computer Engineering Department,
System in Package and Chip-Package-Board Co-Design
مرتضي صاحب الزماني 1 Detailed Routing. مرتضي صاحب الزماني 2 Greedy Routing “ A greedy channel router ”, Rivest, Fiduccia, Proceedings of the nineteenth.
An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.
EE4271 VLSI Design VLSI Channel Routing.
VLSI Physical Design Automation
Computing and Compressive Sensing in Wireless Sensor Networks
Algorithm design techniques Dr. M. Gavrilova
Prepared by Chen & Po-Chuan 2016/03/29
Richard Anderson Lecture 13 Divide and Conquer
EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.
Detailed Routing مرتضي صاحب الزماني.
VLSI Physical Design Automation
Dynamic Programming.
Presentation transcript:

Optimal Bus Sequencing for Escape Routing in Dense PCBs H.Kong, T.Yan, M.D.F.Wong and M.M.Ozdal Department of ECE, University of Illinois at U-C ICCAD 07

Outline Introduction Problem Formulation Optimal LCIS Algorithm Experimental Results Conclusions

Introduction The shrinkage of die sizes and the increase in functional complexities have made circuit designs more and more dense. Boards and packages have reduced in size while the pin counts have been increasing. Traditional routing algorithms cannot handle the new challenges effectively.

Introduction The PCB routing problem can be decomposed into two separate problems: (1) routing nets from pin terminals to component (MCM, memory, etc.) boundaries, which is called escape routing. (2) routing nets between component boundaries, which is called area routing. Only discuss the escape routing problem for a single layer.

Introduction (1) (2)

Introduction Previous escape routing algorithms are net-centric. However, in industrial routing solutions, nets are usually organized in bus structures, and nets in a bus are expected to be routed together without foreign wires in between. Directly applying the net-centric algorithms to all the buses will result in mixing nets of different buses together.

Introduction A sample net-centric escape routing solution for a problem with two buses. Nets of these two buses are mixed up.

Introduction The escape routing problem is bus-centric and can be divided into two subproblems: 1)Finding a subset of buses that can be routed on the same layer without net mixings and crossings, which is the bus sequencing problem.. 2)Finding the escape routing solution for each chosen bus, which can be solved by a net-centric escape router.

Problem Formulation A bus is a group of 2-pin nets, and it has a pin cluster in each component. For each bus, its projection interval on a component can be obtained by projecting the bounding box of its pin cluster onto the component boundary. The nets of a bus typically escape a component from its projection interval.

Problem Formulation For the buses chosen to be routed together, their intervals in each component should have no overlapping. Intervals of buses B, C and D overlap in component 1, so they do not form a sequence. But intervals of buses B, D and E do form a sequence in component 1.

Problem Formulation The two sequences of intervals should have the same ordering; otherwise their nets have crossings. in component 1, but those in component 2 correspond to. A common interval sequence is a bus interval sequence existing on both components, such as.

Problem Formulation The weight of a bus is the number of its nets. Problem definition: Given a bus set B={b 1,b 2,…,b n }, its corresponding intervals on the left side are L={l 1,l 2,…,l n } and the intervals on the right side are R={r 1,r 2,…,r n }. Each bus b i also has a weight w i. The Longest Common Interval Sequence(LCIS) problem is to find a common interval sequence of L and R such that the total weight of the corresponding buses is maximized. This total weight is denoted as LCIS(L, R).

Problem Formulation The net-centric algorithm is applied to the buses chosen by the bus sequencing algorithm one by one. A net-centric escape routing solution for bus D.

Optimal LCIS Algorithm Assume all intervals are parallel with the y axis, where the y coordinates increase from top to bottom. Each interval : lower endpoint. : upper endpoint.

Optimal LCIS Algorithm For a bus b i, define the set of buses above its lower endpoints on both sides as its above set A i : Define the set of buses above its upper endpoints on both sides as its strictly above set SA i :

Optimal LCIS Algorithm For a bus b i, define the longest common interval sequence length LCIS(b i ) as the longest length of the common interval sequence that are above the lower endpoint of b i. A 2 = {b 1,b 3,b 6 } SA 2 = {b 1,b 6 }

Optimal LCIS Algorithm

max b j SA i LCIS(b j ) max b k A i LCIS(b k ) Compare max b j SA i LCIS(b j )+w i with max b k A i LCIS(b k ) UPPER[j] max LCIS(b i )

An Example 8>5, 3<5

Experimental Results

Conclusion Introduce a new optimization problem called the Longest Common Interval Sequence (LCIS) problem and formulated the bus sequencing problem as an LCIS problem. The LCIS algorithm can find an optimal solution in O(nlogn) which is a lower-bound for this problem.