CSE 370 – Winter 2002 - Sequential Logic-2 - 1 Overview Last lecture Intro to FSM’s Counters Today Counters (a little more) Finite state machines (Moore and Mealy examples) 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 1

CSE 370 – Winter 2002 - Sequential Logic-2 - 2 Another example Shift register input determines next state In C1 C2 C3 N1 N2 N3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 100 110 111 011 101 010 000 001 1 N1 := In N2 := C1 N3 := C2 D Q IN OUT1 OUT2 OUT3 CLK 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 2

More complex counter example repeats 5 states in sequence not a binary number representation Step 1: derive the state transition diagram count sequence: 000, 010, 011, 101, 110 Step 2: derive the state transition table from the state transition diagram 010 000 110 101 011 Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 – – – 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 – – – 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 – – – note the don't care conditions that arise from the unused state codes 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 3

More complex counter example (cont’d) Step 3: K-maps for next state functions 0 0 X 1 0 X A B C C+ 1 1 X 0 0 X X 1 A B C B+ 0 1 X 1 0 X X 0 A B C A+ C+ := A B+ := B' + A'C' A+ := BC' 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 4

Self-starting counters (cont’d) Re-deriving state transition table from don't care assignment 0 0 1 1 A B C C+ 1 1 1 0 0 1 A B C B+ 0 1 0 0 A B C A+ 010 000 110 101 011 001 111 100 Present State Next State C B A C+ B+ A+ 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 5

Self-starting counters Start-up states at power-up, counter may be in an unused or invalid state designer must guarantee that it (eventually) enters a valid state Self-starting solution design counter so that invalid states eventually transition to a valid state may limit exploitation of don't cares 010 000 110 101 011 001 111 100 implementation on previous slide 010 000 110 101 011 001 111 100 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 6

CSE 370 – Winter 2002 - Sequential Logic-2 - 7 Finite state machines FSM: A system that can visit only a finite number of logically distinct states Counters are simple FSMs Outputs and states are identical Counters visit states in a fixed sequence FSM behavior can be more complex than counting Outputs and next state can depend on input and present state 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 7

CSE 370 – Winter 2002 - Sequential Logic-2 - 8 State machine model Values stored in registers represent the state of the circuit Combinational logic computes: next state function of current state and inputs outputs function of current state and inputs (Mealy machine) function of current state only (Moore machine) Inputs Outputs Next State Current State output logic next state logic 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 8

State machine model (cont’d) States: S1, S2, ..., Sk Inputs: I1, I2, ..., Im Outputs: O1, O2, ..., On Transition function: Fs(Si, Ij) Output function: Fo(Si) or Fo(Si, Ij) Inputs Outputs Next State Current State output logic next state logic 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 9

Moore versus Mealy machines Moore machine Outputs are a function of current state Outputs change synchronously with state changes outputs state feedback inputs reg combinational logic for next state logic for outputs inputs outputs state feedback reg combinational logic for next state logic for outputs Mealy machine Outputs depend on state and on inputs Input changes can cause immediate output changes *asynchronous* 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 10

Example: Moore versus Mealy machines Circuits recognize AB = 01 What kinds of machines are they? B out A D Q B A clock out D Q clock out A B 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 11

Moore versus Mealy machines (ct’ed) Circuits recognize AB = 10, then AB=01 What kinds of machines are they? D Q A B clock out D Q A B clock out 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 12

FSM design is generalized counter design Counter-design procedure 1. State diagram 2. State-transition table 3. Next-state logic minimization 4. Implement the design FSM-design procedure 1. State diagram and state-transition table 2. State minimization 3. State assignment (or state encoding) 4. Next-state logic minimization 5. Implement the design 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 13

Example: A parity checker Serial input string OUT=1 if odd # of 1s in input OUT=0 if even # of 1s in input 1. State diagram and state-transition table Present Input Next Present State State Output Even 0 Even 0 Even 1 Odd 0 Odd 0 Odd 1 Odd 1 Even 1 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 14

Example: A parity checker (con’t) 2. State minimization: Already minimized Need both states (even and odd) Use one flip-flop 3. State assignment (or state encoding) Present Input Next Present State State Output 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 15

Example: A parity checker (con’t) 4. Next-state logic minimization Assume D flip-flops Next state = (present state) XOR (present input) Present output = present state 5. Implement the design 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 16

Real-life FSM implementation We can map our FSMs to programmable logic devices Macro-cell = DFF + two-level logic Other mapping options: Gate arrays, semicustom ICs, etc. D Q Q 12/2/2018 CSE 370 – Winter 2002 - Sequential Logic-2 - 17