Chapter 4: Instructions Slides to Accompany Assembly Language for Intel-Based Computers, Third Edition Irvine: Assembly Language for Intel-Based Computers (1999)

Arithmetic Instructions INC and DEC ADD SUB Flags affected by ADD and SUB Irvine: Assembly Language for Intel-Based Computers (1999)

Irvine: Assembly Language for Intel-Based Computers (1999) INC and DEC INC adds 1 to destination operand DEC subtracts 1 from destination operand (both) operand can be either a register or variable Carry flag not affected Irvine: Assembly Language for Intel-Based Computers (1999)

Irvine: Assembly Language for Intel-Based Computers (1999) INC and DEC Examples .data membyte db 25 memword dw 36 doubleVal dd 12340000h .code inc al dec bx inc eax inc membyte inc memword dec doubleVal Irvine: Assembly Language for Intel-Based Computers (1999)

Irvine: Assembly Language for Intel-Based Computers (1999) ADD Instruction ADD destination, source Adds source operand to destination operand Source is unchanged and destination is assigned the sum Affects the Carry, Overflow, Sign and Zero flags source operand can be register, immediate value, or memory destination operand can be register or memory only one operand can be a memory operand Irvine: Assembly Language for Intel-Based Computers (1999)

ADD Instruction Examples .data membyte db 25 memword dw 36 doubleVal dd 12340000h .code add al,5 add bx,ax add eax,edx add membyte,al add memword,bx add doubleVal,edx Irvine: Assembly Language for Intel-Based Computers (1999)

Irvine: Assembly Language for Intel-Based Computers (1999) SUB Instruction SUB destination, source Subtracts source operand from destination operand The source operand is first negated and then added to the destination. Affects the Carry, Overflow, Sign and Zero flags source operand can be register, immediate value, or memory destination operand can be register or memory only one operand can be a memory operand Irvine: Assembly Language for Intel-Based Computers (1999)

SUB Instruction Examples .data membyte db 25 memword dw 36 doubleVal dd 12340000h .code sub al,5 sub bx,ax sub eax,edx sub membyte,al sub memword,bx sub doubleVal,edx Irvine: Assembly Language for Intel-Based Computers (1999)

Flags Affected by ADD and SUB After the instruction has executed,... If the destination is zero, the Zero flag is set If the destination is negative, the Sign flag is set If there was a carry out of the highest bit of the destination, the Carry flag is set If the signed result is too small or too large to fit in the destination, the Overflow flag is set Irvine: Assembly Language for Intel-Based Computers (1999)

Irvine: Assembly Language for Intel-Based Computers (1999) Signed Overflow Signed overflow occurs when adding two signed integers, if and only if... both operands are positive, or both operands are negative and the sign of the sum is opposite to the sign of the values being added mov al,+127 add al,+1 ; AL = 80h (-128), Overflow Irvine: Assembly Language for Intel-Based Computers (1999)

Signed Overflow Examples mov al,+127 add al,+1 ; AL = 80h (-128), Overflow mov dx,-32768 ; DX = 8000h (-32768) add dx,-1 ; DX = 8001h, Overflow sub dx,1 ; DX = 8001h, Overflow Irvine: Assembly Language for Intel-Based Computers (1999)

Irvine: Assembly Language for Intel-Based Computers (1999) Basic Operand Types Irvine: Assembly Language for Intel-Based Computers (1999)

Irvine: Assembly Language for Intel-Based Computers (1999) ADC and SBB Instructions Irvine: Assembly Language for Intel-Based Computers (1999)

ADC and SBB Instructions ADC dest,source ; add (source + CF) to destination SBB dest,source ; subtract (source + CF) from destination STC ; set carry flag CLC ; clear carry flag Irvine, Kip R. Assembly Language for Intel-Based Computers.

Adding Two 64-bit Quadwords title QuadWord Addition (QWADD.ASM) ; This program adds two quadword operands. .model small .stack 100h .386 ; enable 32-bit registers .data op1 dq 0A2B2A406B7C62938h op2 dq 080108700A64938D2h result dd 3 dup(?) .code main proc mov ax,@data mov ds,ax mov si,offset op1 mov di,offset op2 mov bx,offset result mov cx,2 ; number of dwords call Multi32_Add mov ax,4C00h int 21h main endp Irvine, Kip R. Assembly Language for Intel-Based Computers.

Adding Two 64-bit Quadwords ; Multi32_Add ; Add two integers, consisting of multiple doublewords. Input ; parameters: SI and DI point to the two operands, BX points to ; the destination operand and CX contains the number of ; doublewords to be added. .code Multi32_Add proc pusha clc ; clear the Carry flag L1: mov eax,[si] ; get the first operand adc eax,[di] ; add the second operand pushf ; save the Carry flag mov [bx],eax ; store the result add si,4 ; advance all 3 pointers add di,4 add bx,4 popf ; restore the Carry flag loop L1 ; repeat loop Irvine, Kip R. Assembly Language for Intel-Based Computers.

Adding Two 64-bit Quadwords ; store the high-order doubleword of the sum mov dword ptr [bx],0 adc dword ptr [bx],0 ; add leftover carry popa ret Multi32_Add endp end main Irvine, Kip R. Assembly Language for Intel-Based Computers.

Subtracting QuadWord Values .data op1 dq 20403004362047A1h op2 dq 055210304A2630B2h result dq 0 ; result = 1A EE 1F D3 EB FA 16 EF .code mov cx,8 ; loop counter: 8 bytes mov si,0 ; set index to 0 clc ; clear Carry flag L1: mov al,byte ptr op1[si] sbb al,byte ptr op2[si] mov byte ptr result[si],al inc si loop L1 Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. Multiplication AL, AX, EAX are implied destination operands Source operand can be a register or variable 16-bit output is AX 32-bit output is DX:AX 64-bit output is EDX:EAX Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. MUL Instruction 8-bit multiplication: MUL BL ; product = AX 16-bit multiplication: MUL DX ; product = DX:AX 32-bit multiplication: MUL ECX ; product = EDX:EAX Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. MUL (Flags) Carry and Overflow flags are set when the product extends into its high register: mov ax,5000h mov bx,10h mul bx ; DX:AX = 00050000h ; CF=1, OF=1 Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. MUL Examples mov al,5 mov bl,10h mul bl ; AX = 0050h mov ax,500h mov bx,100h mul bx ; DX:AX = 00050000h mov eax,12345678h mov ebx,10000h mul ebx ; EDX:EAX = 0000123456780000h Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. MUL Examples (2) You can save the 64-bit product in a Quadword variable by storing each doubleword separately: .data productQ DQ ? .code mov eax,12345678h mov ebx,10000h mul ebx ; EDX:EAX = 0000123456780000h mov dword ptr productQ, eax mov dword ptr productQ+4, edx Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. IMUL Instruction Use with signed operands Sign-extends the result into the high register CF=1 and OF=1 if the sign of the high register is different from the sign of the low register Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. IMUL Examples mov al,-4 mov bl,4 imul bl ; AX = FFF0h (-16), CF=0, OF = 0 mov al,48 mov bl,4 imul bl ; AX = 00C0h (+192), CF=1, OF = 1 Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. IMUL Examples (2) mov ax,-128 mov bx,4 imul bx ; DX:AX = FFFFh,FFE0h (-512) ; CF=0, OF = 0 Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. DIV Instruction Dividiend is AX, DX:AX, or EDX:EAX Divisor can be 8-bit, 16-bit, 32-bit register or variable Quotient is AL, AX, or EAX Remainder is AH, DX, or EDX Status flag values are undefined Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. DIV Examples mov ax,0083h ; dividend mov bl,2 ; divisor div bl ; AL = 41h, AH = 01h mov dx,0 ; dividend, high mov ax,8003h ; dividend, low mov cx,100h ; divisor div cx ; AX = 0080h, DX = 0003h Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. Divide Overflow Happens when the quotient is too large to fit in the destination register. Causes a processor interrupt. mov dx,0050h ; dividend, high mov ax,0000h ; dividend, low mov cx,10h ; divisor div cx ; quotient= 50000h, cannot ; fit in AX register Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. IDIV Instruction Use for signed division Dividend must be sign-extended before executing the IDIV instruction: CBW extends AL into AH CWD extends AX into DX CDQ extends EAX into EDX Status flag values are undefined Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. IDIV Examples mov ax,-257 ; dividend mov bl,2 ; divisor idiv bl ; AL = -128, AH = -1 mov ax,-5000 ; dividend cwd ; extend into DX mov bx,256 ; divisor idiv bx ; AX = -19, DX = -136 Irvine, Kip R. Assembly Language for Intel-Based Computers.

Irvine, Kip R. Assembly Language for Intel-Based Computers. IDIV Examples (2) mov eax,-500002 ; low part of dividend cdq ; extend into EDX mov ebx,100 ; divisor idiv ebx ; EAX = -5000, EDX = -2 Irvine, Kip R. Assembly Language for Intel-Based Computers.