EEC4113 Data Communication & Multimedia System Chapter 5: Error Control by Muhazam Mustapha, August 2010

Learning Outcome By the end of this chapter, students are expected to be able to mathematically understand and explain the various methods in error detections and corrections.

Chapter Content Type of Error Error Detection Error Correction

Type of Errors

Types of Errors In digital transmission systems, an error occurs when a bit is altered between transmission and reception. Binary 1 was transmitted but binary 0 is received, or vice versa. 2 general types of errors can occur: Single bit errors Burst errors

Single Bit Error Isolated error condition. 0 changed to 1 1 1 1 Sent Received Isolated error condition. Alters one bit but does not affect nearby bits. Usually due to white noise.

Burst Error Contiguous sequence of bits Length of burst error (5 bits) Sent 1 1 1 1 1 Bits corrupted by burst error 1 1 1 1 1 1 1 1 Received Contiguous sequence of bits The first and last bits and any number of intermediate bits are received in error

Burst Error More common more difficult to deal with Can be caused by impulse noise & fading Effects of burst error are greater at higher data rates Consider an impulse noise event of 1μs occurs At a data rate of 10 Mbps, resulting error burst is 10 bits At a data rate of 100 Mbps, resulting error burst is 100 bits

Burst Error For reliable communication, error must be detected and corrected. Additional bits added by transmitter for error detection purposes at receiver Called REDUNDANCY Some methods of error detection: Parity Check CRC

Error Detection

Parity Check Also known as Vertical Redundancy Check Single parity bit is attached to the bit stream to maintain either odd or even number of 1-s Example, for bit stream of 00110011 Even parity: 0 00110011 Odd parity: 1 00110011

Parity Check By convention, even parity is used for synchronous transmission and odd is for asynchronous. Even number of bit errors can never be detected. Most error are long enough to constitute more than just 1 bit – parity check is hardly enough

Longitudinal Redundancy Check Data is arranged in rows and columns An extra row added containing column wise parity bits The LRC row is transmitted following the data rows. Since it contains parity check for bits at distance more than 1 bits, LRC is able to detect burst error.

Longitudinal Redundancy Check 11100111 11011101 00111001 10101001 11100111 11011101 00111001 10101001 10101010 LRC (even parity) 11100111 11011101 00111001 10101001 10101010 send out

Cyclic Redundancy Check (CRC) Most common, most powerful, error-detecting code CRC is used for detection of a single error, more than single error and burst error (when two or more consecutive bits in frame have changed) CRC uses modulo-2 addition to compute the Frame Check Sequence (FCS)

Cyclic Redundancy Check (CRC) Modulo-2 arithmetic uses binary addition and subtraction without carry – which reduce to XOR operation. Example: 1111 + 1010 0101 1111 − 0101 1010 11001 × 11 11001 11001 101011

Cyclic Redundancy Check (CRC) Structure: T = Transmitted frame = n bits D = Data = k bits F = Frame Check Sequence (FCS) = n-k bits P = Predetermined divisor = n-k+1 bits Transmitted Frame Data FCS k bits n-k bits n bits

Cyclic Redundancy Check (CRC) At sender: 2n−kD / P is computed using modulo-2 arithmetic, and the remainder is kept as F Transmit data as 2n−kD + F = T At receiver: The received data T is divided by P using modulo-2 arithmetic. If there is no remainder, then there is no error, otherwise there is.

Cyclic Redundancy Check (CRC) Example: Message, D = 1010001101 Pattern, P = 110101 Length of F = Length of P − 1 = 5 bits = n−k Hence 2n−kD = 101000110100000 Compute 2n−kD / P using modulo-2 arithmetic, then take the remainder as F (next slide)

Cyclic Redundancy Check (CRC) Example (cont): 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 0 1 0 1 1 1 0 0 1 0 1 1 0 1 0 1 Remainder (F) 0 1 1 1 0

Cyclic Redundancy Check (CRC) Example (cont): The transmitted data is then, T = 2n−kD + F 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 + 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 T

Cyclic Redundancy Check (CRC) Example (cont): At receiver 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 Zero remainder 0 0 0 0 0

CRC Pattern Convention The pattern (divisor) is often represented as polynomial instead of binaries. For P = 1101101  x6+x5+x3+x2+1 Some standard polynomials in IEEE and ITU: CRC-12 = x12+x11+x3+x2+x+1 CRC-16 = x16+x15+x2+1 CRC-CCITT = x16+x12+x5+1 CRC-32 = x32+x26+x23+x22+x16+x11+x10+x8+x7+x5+x4+x2+x+1

Error Correction

Error Correction In ARQ protocol, if errors detected, the only way to correct it is by re-sending. In some application this is not appropriate. Furthermore, if the sliding window is too small, the ARQ easily reduces to Stop-and-Wait and time is wasted waiting for time-out.

Error Correction Re-transmission is costly in some application: In high error rate environment, e.g. wireless link, this means many re-transmission In long propagation delay link, e.g. satellite link, this means much longer wait Hence the need for error correcting codes.

Error Correction Process At sender, the data will be added with forward error correction (FEC) code. At receiver, the data with FEC will be decoded with any of the following case: No error detected Error detected and correctable Error detected but not correctable Some error could not even be caught

Error Correction Process Some error correcting schemes: Multidimensional parity check (e.g. LRC) Hamming Code Reed-Solomon Code Reed-Muller Code

Multidimensional Parity Check LRC (2 dimensional) can be used to develop error correcting code. In each row there would be a parity check attached. An extra parity row would be added as normal. Any single bit error would be able to be corrected by checking the mismatch parity in row and column.

LRC Error Correction even parity 11100111 11011101 00101000 10101001 11100111 11011101 00101000 10101001 11100111 11011101 00101000 10101001 SENDER 10111011 LRC (even parity) RECEIVER 11100111 11011101 00001000 10101001 error bit 10111011

Hamming Code At sender: Frame bits are numbered starting from 1 Bit locations with only one binary 1 in its binary form is filled in with parity bits Other locations will be filled with data bits The parity bits will match the parity of the bits at locations with binary form having the binary 1 at same location.

Hamming Code Data to send: 1001101 Even Parity Bit Bit position Bit position (binary) Bit type 1 0001 Parity 2 0010 3 0011 Data 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 Even Parity Actual Frame sent: 10011100101

Hamming Code At receiver: The re-matched parities are the respective positions. Syndrome: If the re-matching results in 0000, then there is no error If the re-matching results in a bit location with one binary 1, then error is in parity location – ignore If the re-matching results in a bit location with more than one binary 1, then error is in data location – toggle the error If the re-matching results in a bit location beyond the used locations, then the error is not correctable

Hamming Code At receiver error Parity re-matching Error at bit 6 Bit Bit position Bit position (binary) Bit type 1 0001 Parity 2 0010 3 0011 Data 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 error Parity re-matching 0110 Error at bit 6