INFN - Padova michele.michelotto at pd.infn.it

Slides:



Advertisements
Similar presentations
Hepmark Valutazione della potenza dei nodi di calcolo nella HEP Michele Michelotto Padova Ferrara Bologna.
Advertisements

Alessandro Italiano INFN – CNAF 26/09/2003 1/5 Status of the INFN - EDG testbeds Alessandro Italiano 7th DataGrid Conference.
Concurrent programming: From theory to practice Concurrent Algorithms 2014 Vasileios Trigonakis Georgios Chatzopoulos.
Intel Multi-Core Technology. New Energy Efficiency by Parallel Processing – Multi cores in a single package – Second generation high k + metal gate 32nm.
Hepmark project Evaluation of HEP worker nodes Michele Michelotto at pd.infn.it.
OPTERON (Advanced Micro Devices). History of the Opteron AMD's server & workstation processor line 2003: Original Opteron released o 32 & 64 bit processing.
INTEL COREI3 INTEL COREI5 INTEL COREI7 Maryam Zeb Roll#52 GFCW Peshawar.
S. Narayanasamy, Z. Wang, J. Tigani, A. Edwards, B. Calder UCSD and Microsoft PLDI 2007.
Computing Resources Joachim Wagner Overview CNGL Cluster MT Group Cluster School Cluster Desktop PCs.
Performance benchmark of LHCb code on state-of-the-art x86 architectures Daniel Hugo Campora Perez, Niko Neufled, Rainer Schwemmer CHEP Okinawa.
HS06 on the last generation of CPU for HEP server farm Michele Michelotto 1.
Moving out of SI2K How INFN is moving out of SI2K as a benchmark for Worker Nodes performance evaluation Michele Michelotto at pd.infn.it.
Processors Menu  INTEL Core™ i Processor INTEL Core™ i Processor  INTEL Core i Processor INTEL Core i Processor  AMD A K.
K10 based AMD processors Dezső Sima Fall 2007 (Ver. 2.1)  Dezső Sima, 2007.
SouthGrid Status Pete Gronbech: 4 th September 2008 GridPP 21 Swansea.
Different CPUs CLICK THE SPINNING COMPUTER TO MOVE ON.
RIDGE Version II (Radar Integrated Display with Geospatial Elements) NOAA Systems of Systems Workshop – October 6-7, 2009 – RIDGE Team  RIDGE Version.
F. Brasolin / A. De Salvo – The ATLAS benchmark suite – May, Benchmarking ATLAS applications Franco Brasolin - INFN Bologna - Alessandro.
Intel’s Penryn Sima Dezső Fall 2007 Version nm quad-core -
Processor Development The following slides track three developments in microprocessors since Clock Speed – the speed at which the processor can carry.
Sandor Acs 05/07/
1 PRAGUE site report. 2 Overview Supported HEP experiments and staff Hardware on Prague farms Statistics about running LHC experiment’s DC Experience.
HS06 on new CPU, KVM virtual machines and commercial cloud Michele Michelotto 1.
Hyper Threading Technology. Introduction Hyper-threading is a technology developed by Intel Corporation for it’s Xeon processors with a 533 MHz system.
Microprocessors BY Sandy G.
Sep. 17, 2002BESIII Review Meeting BESIII DAQ System BESIII Review Meeting IHEP · Beijing · China Sep , 2002.
HS06 on last generation of HEP worker nodes Berkeley, Hepix Fall ‘09 INFN - Padova michele.michelotto at pd.infn.it.
PROOF tests at BNL Sergey Panitkin, Robert Petkus, Ofer Rind BNL May 28, 2008 Ann Arbor, MI.
HS06 performance per watt and transition to SL6 Michele Michelotto – INFN Padova 1.
HEPMARK2 Consiglio di Sezione 9 Luglio 2012 Michele Michelotto - Padova.
Industry Standard Servers Infrastructure Refresh Why?
From Westmere to Magny-cours: Hep-Spec06 Cornell U. - Hepix Fall‘10 INFN - Padova michele.michelotto at pd.infn.it.
Michele Michelotto – CCR Marzo 2015 Past present future Fall 2012 Beijing IHEP Spring 2013 – INFN Cnaf Fall 2013 – Ann Arbour, Michigan Univ. Spring.
New CPU, new arch, KVM and commercial cloud Michele Michelotto 1.
The last generation of CPU processor for server farm. New challenges Michele Michelotto 1.
DGAS Distributed Grid Accounting System INFN Workshop /05/1009, Palau Giuseppe Patania Andrea Guarise 6/18/20161.
PASTA 2010 CPU, Disk in 2010 and beyond m. michelotto.
Hardware Architecture
Moving out of SI2K How INFN is moving out of SI2K as a benchmark for Worker Nodes performance evaluation Michele Michelotto at pd.infn.it.
CVMFS Alessandro De Salvo Outline  CVMFS architecture  CVMFS usage in the.
BeStMan/DFS support in VDT OSG Site Administrators workshop Indianapolis August Tanya Levshina Fermilab.
SI2K and beyond Michele Michelotto – INFN Padova CCR – Frascati 2007, May 30th.
Benchmarking of CPU models for HEP application
Brief introduction about “Grid at LNS”
Evaluation of HEP worker nodes Michele Michelotto at pd.infn.it
CCR Autunno 2008 Gruppo Server
Hardware 201: Selecting Database Hardware
Gruppo Server CCR michele.michelotto at pd.infn.it
INFN - Padova michele.michelotto at pd.infn.it
LCG Service Challenge: Planning and Milestones
Worker Node per HEP – Technology update
Solid State Disks Testing with PROOF
How to benchmark an HEP worker node
Games Programming in Scratch
Moroccan Grid Infrastructure MaGrid
Low Power processors in HEP
Gruppo Server CCR michele.michelotto at pd.infn.it
How INFN is moving out of SI2K has a benchmark for Worker Nodes
RT2003, Montreal Niko Neufeld, CERN-EP & Univ. de Lausanne
Passive benchmarking of ATLAS Tier-0 CPUs
UTFSM computer cluster
Chapter 6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism Topic 11 Amazon Web Services Prof. Zhang Gang
Installation and database instance essentials
What happens inside a CPU?
Aggiornamento sullo stato del Tier-2 di Catania
Infrastructure for testing accelerators and new
Transition to a new CPU benchmark
The Small batch (and Other) solutions in Mantle API
We power your restaurant's growth engine with app fuel.
Building a Balloon Rocket Car
Presentation transcript:

INFN - Padova michele.michelotto at pd.infn.it Outlook Server

Westmere 56xx Programming today is a race between software engineers striving to build bigger and better idiot-proof programs, and the universe trying to build bigger and better idiots. So far, the universe is winning.

Clock with Turbo Mode Off Westmere DP 16 March 2010 first release of Xeon DP on Westmere 32nm model Cores/threads L3 cache Clock with Turbo Mode Off TDP X5680 6/12 12 MB 3.33 GHz 130 W X5670 2.93 GHz 95 W X5660 2.80 GHz X5650 2.66 GHz L5640 2.26 GHz 60 W X5677 4/8 3.46 GHz X5667 3.06 GHz E5640 80 W E5630 2.53 GHz E5620 2.40 GHz L5630 40 W m. michelotto

michele michelotto - INFN HT ON vs HT OFF Ottobre 2010 - CCR michele michelotto - INFN

michele michelotto - INFN Padova 5520 32 bit - HT ON/OFF HT ON:81.81 HT OFF: 95.96 HT OFF is better up to 11concurrent run CCR WS 10 michele michelotto - INFN Padova

michele michelotto - INFN 5650 vs 5670pre-rel? 5650 at 2.66 GHz faster than 5670 pre-release at 2.93 GHz? More evident from 10 to 16 instances Ottobre 2010 - CCR michele michelotto - INFN

AMD Magny-Cours 61xx

Magny-Cours A known bug is better than an unknown feature. Xeon 5670 model Cores/threads L3 cache Clock ACP Xeon 5670 6/12 12 MB 2.93 GHz 95 W 6124 HE 8/8 1.8 GHz 65 W 6128 80 W 6128 HE 2.0 GHz 6134 2.3 GHz 6136 2.4 GHz 6164 HE 12/12 1.7 GHz 6168 1.9 GHz 6172 2.1 GHz 6174 2.2 GHz 6176 SE 105 W A known bug is better than an unknown feature. m. michelotto

michele michelotto - INFN 5650 vs 6136 Ottobre 2010 - CCR michele michelotto - INFN

michele michelotto - INFN thanks Hepmark – INFN - CNS5 2 x 5650 2 x 5520 2 x Opteron 6172. to be delivery Farming Group @ CNAF Andrea Chierici – measurements on 5670 prerelease Radiografia muonica Few days to measures opteron 6136 Ottobre 2010 - CCR michele michelotto - INFN

michele michelotto - INFN Supporto ai referee Working group CCR Formato nell’ultima CCR a Luglio Michele Michelotto, Marco Serra, Alessandro Brunengo Supporto tecnologico ai referee del calcolo delle CSN Andamento del mercato Worker Node, Server, Storage, Overhead Ottobre 2010 - CCR michele michelotto - INFN

michele michelotto - INFN Questions? Ottobre 2010 - CCR michele michelotto - INFN

Feedback: Privacy Policy Feedback
Do Not Sell My Personal Information
About project: SlidePlayer Terms of Service

© 2024 SlidePlayer.com Inc. All rights reserved.