DESIGN AND IMPLEMENTATION OF DIGITAL FILTER TANBIR SEN PURKAYASTHA ELECTRONICS AND COMMUNICATION ENGINEERING Meghnad Saha Institute of Technology, Kolkata- 700150  

OUTLINE Objective Introduction Implementation Platform Proposed Scheme Experimentation, Results and Discussion Conclusion References

OBJECTIVE High Throughput Latency Area Low Power

OBJECTIVE To design and implement a frequency selective digital filters with high speed ,low chip area and low power consumption using VHDL. Frequency selective digital filters are required in most DSP applications. To obtaining high speed, low cheap area as well as low power consumption fixed algorithm and co-optimized implementation of the DSP part are preferable whenever possible. This co-optimization reduces the power consumption of the circuit with atleast one order of magnitude compare to flexible implementation.

INTRODUCTION Frequency selective digital filters are required in most DSP (digital signal processing) applications. The requirements on high data rates in many communication systems, the corresponding subsystems and circuits must have a high speed. The increasing use of portable equipment together with the cost of cooling electronic equipment will be a strong incentive to increase the efforts of reducing the power consumption in the DSP (sub) systems. The design of DSP algorithm and hardware co-design with the aim of obtaining efficient architectures with respect to design effort, chip area, and power consumption.

DIGITAL FILTERS The impulse response of digital filter can be divided in to two categories: IIR (infinite impulse response) FIR (Finite impulse response) The former correspond to general case described by the equation below while the latter occurs when N=0.

FIR FILTERS Where ck = bk/a0 are the coefficient of FIR filter . This equation can be obtained by the system Where ck = bk/a0 are the coefficient of FIR filter . Only FIR Filter can exhibits linear phase, so they are indispensable when linear phase are required, like in many telecom applications.

IMPLEMENTATION PLATFORM Fig. Where D (delay) represented a register (flip flops), a triangle is a multiplier, and a circle means an adder.

REALIZATION OF FIR FILTER The system function of FIR filter can be written as H (Z) =∑ h (n)z-n for n=0 to N-1. =h(0) + h(1) z-1 + h(2)z-2 …….+h(N-1)z-(N-1) Y(Z)=h(0)X(Z)+ h(1)z-1X(Z)+ h(2)z-2X(Z)+ ……. h(N-1)z-(n-1) X(Z) This equation is realized in below fig. This is known as transversal structure

PERFORMANCE PARAMETERS The performance of fir filter can be measured in terms of :- Latency :-The latency for an operation is defined as the time required for an input of a given significance level to affect the output at the same significance level Area :-As the modern electronics devices become smaller and smaller so chip area is an important design parameter for any electronics circuits. Power:-Power consumption in the circuits is also related to the chip area. If the chip area is increased then Power consumption will also increased in the circuits as well. The design and implementation of fir filter using VHDL is done to meet the above parameter in order to achieve the minimum chip area and low power consumption which uses different arithmetic based on implementation platform.

PROPOSED SCHEME BIT PARALLEL ARITHMETIC: The fir filter designed by using this arithmetic will have high computational speed BIT SERIAL ARITHMETIC : The fir filter designed by using the serial arithmetic will have low power consumption and minimum chip area.

VHDL - THE LANGUAGE VHSIC(Very High Speed Integrated Circuit) Hardware Description Language . It provides a versatile set of description facilities to model DSP circuits from the system level to the gate level It describe a logic circuit by function data flow behaviour and structure. It can be used as a general purpose programming language ie a ommands which correspond to logic gates are executed in parallel as soon as a new input arrives.

USING BIT-PARALLEL ARITHMETIC Inputs to a bit-parallel arithmetic operation are stored in registers. All bits are conceptually processed at once, i.e., all bits in the inputs are applied in parallel and all of the bits in the output occur simultaneously and the obtained output is stored in the registers. The fir filter designed by using this arithmetic will have high computational speed .

SUB- BLOCKS Bit parallel arithmetic can be designed by using different sub-blocks They are :- Sixteen Bit Full Adder Booth Multiplier

SIXTEEN-BIT FULL ADDER To design a 16 bit full adder, first a single bit three input adder is created .By port mapping the ports of this three input adder block 16 bit full adder is created. This generic VHDL code of 16 bit full adder is used as a library component

SIXTEEN-BIT FULL ADDER VHDL Test bench wave form

RTL of booth multiplier Is One of the solutions of realizing high speed multipliers is to enhance parallelism which helps to decrease the number of subsequent calculation stages. The low power consumption quality of booth multiplier makes it a preferred choice in designing different circuits RTL of booth multiplier

BOOTH MULTIPLIER VHDL Test bench wave form

FIR FILTER -(bit parallel arithmetic) VHDL Test bench wave form

BIT-SERIAL ARITHMETIC In bit-serial arithmetic one bit of the input data is processed in each clock cycle, generally starting with the LSB. The complexity of an operation is low as there are few input bits to operate on in each clock cycle. Use of bit-serial arithmetic results in small processing elements and short interconnection paths between the processing elements .

SUB-BLOCKS IN BIT-SERIAL ARITHMETIC In bit-serial arithmetic the bits are first stored in registers serial fashion. The sub-blocks required for designing fir filter using serial arithmetic are:- Serial adder Serial-parallel multiplier Delay

SERIAL ADDER To implement this adder we need the memory block to store the sum and carry, for that we use D flip flops. In this adder circuit carry output of present state is feed back as input to the previous state. Here the reset bit is used to reset the output. Output is not available in the output port until the set bit is in on state. RTL Schematic

WAVEFORM OF SERIAL ADDER VHDL Test bench wave form

SERIAL-PARALLEL MULTIPLIER One of the input vector ‘a’ is applied serially to the circuit (one bit at a time starting from the LSB), while the other ‘b’ is applied parallel.(all bit simultaneously).Say that ‘a’ has M bit while ‘b’ has N. Then after all M bit of ‘a’ have been presented to the system a string of M ‘0’s must follows , in order to complete M+N bit output product. RTL Schematic

WAVEFORM OF S\P MULTIPLIER VHDL Test bench wave form

DELAY Under processing RTL Schematic

DELAY VHDL Test bench wave form

FIR OUTPUT- (bit SERIAL arithmetic) RTL Schematic

FIR OUTPUT- (bit SERIAL arithmetic) VHDL Test bench wave form

PERFORMANCE ANALYSIS Depending on two different bit-arithmetic that is bit-parallel and bit-serial arithmetic the performance analysis of fir filter has been done. This analysis comprises :- Power Analysis Design summary Area Analysis Latency.

POWER ANALYSIS POWER CONSUMPTION: . Power consumption is lower in the bit-serial case compared to bit- parallel implementation because the chip area of the circuit is smaller, and the output is correctly computed directly without excessive switching.

POWER SUMMARY Total estimated power summary of Direct form realization of FIR filters. Using bit parallel arithmetic 0.090w Using bit serial arithmetic 0.084w According to the summary total power consumption is the sum of quiescent power, logic power, IO power & digital clock manager power

DESIGN SUMMARY OF BIT-PARALLEL ARITHMETIC Number of Slices Flip Flops 34 Number of 4 input LUTs 479 Number of occupied slices 271 Number of bonded INPUT/OUTPUT 26

DESIGN SUMMARY OF BIT-SERIAL ARITHMETIC Number of Slices Flip Flops 78 Number of 4 input LUTs 73 Number of occupied slices 47 Number of bonded INPUT/OUTPUT 13

AREA ANALYSIS Area can be analyzed If a comparison is made between these two design summery, then it is found that bit parallel arithmetic realization have used more number of 4 input LUTs, more number of occupied slices, more number of bonded INPUT/OUTPUT compared to bit serial realization. Extra number of LUTs used are (479-73) =406, extra number of occupied slices are (271-47) =224, extra number of bonded INPUT/OUTPUT are (26-13) =13.

AREA SUMMARY From this comparison it is found that bit parallel implementation of Direct form realization will need more chip area compared to bit serial implementation. As the modern electronics devices become smaller and smaller so chip area is an important design parameter for any electronics circuits. If the design is considered in terms of chip area, then bit serial implementation of this digital Filter is advantageous compared to the bit parallel implementation of digital filters.

LATENCY The computational speed is characterized by latency. The latency for an operation is defined as the time required for an input of a given significance level to affect the output at the same significance level . It describes how long time it takes for an input value to be transformed into an output value. It is often convenient to measure the latency in terms of clock cycles instead of real time unit. Latency depends on the function of the processing element (PE).

LATENCY IN BIT PARALLEL In case of bit parallel arithmetic although there is initial latency in each output but the output bit of a stage (y15 to y0) appears in synchronous with clock pulse. So we get LSB to MSB output data of a stage within a single clock pulse. Depending on latency the computational speed of bit-parallel arithmetic is faster.

LATENCY IN BIT SERIAL In bit serial arithmetic the data are feed serially, first the LSB is given then in the next clock pulse second bit is given. In this way the data of all input variables are feed and we get the output in the same fashion. This way of entering input data and extracting output data will introduced latency in the output waveform. As the latency is go on increasing in every individual output, so it will take time for the last bit (MSB) of each output to appear in the waveform. The last bit (MSB) of output ‘y0’ is situated in 200 to 250 ns and the last bit (MSB) of ‘y1’ is situated in 450 to 500 ns.

ADVANTAGE AND DISADVANTAGE OF BIT-PARALLEL ARITHMETIC An advantage of bit-parallel arithmetic is that the amount of work performed by a processing element during one clock cycle is relatively large, and the clock frequency can therefore be kept low. It means it has high computational speed. Disadvantage of bit-parallel arithmetic is that it has high power consumption and chip area as compared to bit- serial arithmetic

ADVANTAGE AND DISADVANTAGE OF BIT-SERIAL ARITHMETIC Power consumption: bit serial digital filters have less power consumption because of serial parallel multiplier chip area : it consumes smaller area compared to bit parallel Disadvantage Design complexity: The design time for the bit-serial system increases due to the higher complexity of timing the bit-serial streams. Speed: The potential performance of bit-serial processing elements may be somewhat degraded due to practical problems with high frequency clocking.

COMPARATIVE STUDY By making a comparative study among all this Filters to estimate the performance in terms of From these performances it is found that Simulation time - bit parallely implemented digital filters take less time compared to bit serial implementation. Initial latency - bit serially designed filters have higher initial latency compared to bit parallel implemented filters. simulation time, chip area and power consumption, several important performances are observed. Chip area - bit parallel implementation of digital filters consume much larger area compared to the same filters realized using bit serial arithmetic . Power consumption - bit serial digital filters have less power consumption than bit parallel implementation.

CONCLUSION In this project we have presented an approach to design and implement very fast fixed-function digital filters using bit-serial arithmetic and bit-parallel arithmetic with high speed and low power consumption. The increased speed and decreased area can be traded for reduced power consumption through power supply voltage scaling. A third-order lattice wave digital filter will be implemented to estimate the performance in terms of chip area and power consumption in comparison with state-of-the-art designs based on traditional techniques.