Structural style Modular design and hierarchy Part 1 IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology

Advantages of good design partition Design management is easier Modules can be designed and verified by different individuals Maximum reuse of modules is made possible The design description is more readable and easier comprehend Verification is simplified Better design results are likely The portability of the design is enhanced

Hierarchy tree for the modular partition There are tradeoffs in deciding the complexity of a leaf nodes, such as code readability and maintainability, module reuse, and synthesis and verification efficiency.

A simple example (full adder) Modular and hierarchical designs are implemented in VHDL using structural style architectures. A structural architecture is, ultimately, a collection of design entities interconnected by signals.

Hierarchy tree for a full adder The partitioning process is continued until each leaf node represents a relatively simple module that we can easily comprehend and directly code.

Hierarchy tree for a full adder Ultimately, the lowest level components in a structural design must each be described behaviorally (dataflow and behavioral styles) in their respective architectures. Otherwise, the top-level description cannot be compiled, simulated, or synthesized.

Design Entity design entity entity declaration architecture 1 Design Entity - most basic building block of a design. One entity can have many different architectures.

Design file and design units A name made directly visible to a primary library unit by a context clause is automatically visible in any associated secondary library unit.

Half-adder structural implementation Half-adder structural implementation using XOR and AND design entities u1: entity xor_2 port map (i1 => a, i2 => b, o1 => sum); Ccomponent instantiation statements are concurrent statements. An event on any signal associated with a design entity’s inputs (in its port map) causes the design entity to “execute.” In the structural half-adder example, an event on either input a or b causes each design entity to simultaneously update its output value.

Positional and named association Using named association, each association is explicit and the listing order of the associations in the port map is of no concern. For example, a design entity instantiated with a port map equivalent to the previous one is: u1: entity xor_2 port map (i2 => b, o1 => sum, i1 => a); Alternatively, we can use positional association to specify how a design entity is connected. Using positional association, signals are associated based on their relative positions as specified in the entity’s declaration. The corresponding component instantiation statement using positional association is: u1: entity xor_2 port map (a, b, sum); While positional association is more concise, named association is preferable because it is more readable and less error prone.

Closer look at structiral design In a structural style description, component instantiation statements are used to create an instance of each design entity. The syntax provides two forms for a component instantiation statement: 1) Direct instantiation of a design entity. 2) Indirect instantiation. Indirect instantiation instantiates a component, which serves as a placeholder for a design entity rather than directly instantiating a design entity. The binding of each component to an actual design entity is then accomplished using either default binding or an explicit binding indication.

Direct entity instantiation library ieee; use ieee.std_logic_1164. all ; entity half_adder is port (a, b : in std_logic; sum, carry_out : out std_logic); end half_add; architecture structure-1 of half_adder is begin u1: entity xor_2 port map (i1 => a, i2 => b, o1 => sum); u2: entity and_2 port map (i1 => a, i2 => b, o1 => carry_out); end structure-1 ; Here we suppose that there are deisgn units xor_2 and and_2 in the library WORK.

Indirect design entity instantiation architecture structure-2 of half_adder is component xor_2 -- xor_2 component declaration port (i1, i2 : in std_logic; o1: out std_logic); end component; component and_2 -- and_2 component declaration begin u1: component xor_2 port map (i1 => a, i2 => b, o1 => sum); u2: component and_2 port map (i1 => a, i2 => b, o1 => carry_out); end structure-2 ;

Design file and design units A design unit is a VHDL construct that that can be independently compiled and stored in a design library. Design units provide modularity for the design management of complex systems. A design file is a source file containing one or more design units. A design file is the input to a VHDL compiler. Design units in a design file are compiled in the same order as their textual order in the file. Using separate files allows separate compilation and verification of each design entity.

Hierarchy tree for a full adder structural description In a structural design each leaf node must be described behaviorally (dataflow and behavioral styles) in their respective architectures.

Description in a single design file -1- library ieee; use ieee.std_logic_1164. all ; entity half_adder is port (a, b : in std_logic; sum, carry_out : out std_logic); end half_add; architecture dataflow of half_adder is begin sum <= a xor b ; carry_out <= a and b ; end dataflow ; entity or_2 is port (a, b : in std_logic; sum, or_out : out std_logic); end or_2; architecture dataflow of or_2 is or_out <= a or b ;

Description in a single design file -2- library ieee; use ieee.std_logic_1164. all ; entity full_adder is port (a, b, carry_in : in std_logic; sum, carry_out : out std_logic) ; end full_add; architecture structure of full_adder is signal s1, s2, s3 : std_logic ; begin ha1 : entity half_adder port map (a => a, b => b, sum => s1, carry_out=>s2); ha2 : entity half_adder port map (a =>s1, b =>carry_in, sum =>sum, carry_out =>s3); or1 : entity or_2 port map (a => s3, b => s2, or_out => carry-out) ; end structure ;

Architecture with indirect instantiation of design entities architecture structure-2 of full_adder is component half_adder is -- component declaration port (a, b : in std_logic; sum, carry_out : out std_logic) ; end component ; component or_2 is -- component declaration port (a, b : in std_logic; carry_out : out std_logic) ; signal s1, s2, s3 : std_logic ; -- signals declaration begin -- component instantiations ha1 : component half_adder port map (a => a, b => b, sum => s1, carry_out=>s2); ha2 : component half_adder port map (a =>s1, b =>carry_in, sum =>sum, carry_out =>s3); or1 : component or_2 port map (a => s3, b => s2, or_out => carry-out) ; end structure-2 ;

Design libraries A simulator can only simulate programs that have been successfully compiled and stored in a library. A design library is a logical storage area in the host computer environment for compiled design units (library units) A design library is identified by its logical name. There are two kinds of design libraries: working library and resource library

Design libraries All VHDL compilers come with the library STD included. This built-in library is provided by standard IEEE Std 1076. Library STD contains two packages: STANDARD and TEXTIO. VHDL compilers also include the library IEEE. This library contains packages defined by VHDL’s supporting standards, such as packages STD_LOGIC_1164. Of course, we can write our own packages and place them in libraries that we create – user-defined libraries. Third-party intellectual property provides sell libraries containing complex design entities that we can use as modules. PLD vendor libraries (Source code for the architecture bodies and package bodies is usually not provided)

Using library units Implicit context clause: Every library unit is assumed to be preceded by the implicit context clause library std, work ; use std.standard.all ; Rules: A primary unit whose name is referenced within a given design unit must be compiled prior to compiling the given design unit. A primary unit must be compiled prior to compiling any associated secondary units. User written packages and other design units can be precompiled and placed in a resource library. Design entities in a resource library can be used as modules by design entities in a design file. The appropriate context clauses for any resource libraries used must be included prior to each library unit in a design file.

Design file containing top-level entity - - The half_adder and OR gate design entities have been - - compiled to a user-created library called parts. library ieee; use ieee.std_logic_1164. all ; library parts ; use parts.all ; entity full_adder is port (a, b, carry_in : in std_logic; sum, carry_out : out std_logic) ; end full_add; architecture structure of full_adder is signal s1, s2, s3 : std_logic ; begin ha1 : entity half_adder port map (a => a, b => b, sum => s1, carry_out=>s2); ha2 : entity half_adder port map (a =>s1, b =>carry_in, sum =>sum, carry_out =>s3); or1 : entity or_2 port map (a => s3, b => s2, or_out => carry-out) ; end structure ;

GENERATE statement 4 bit equality comparator example

Structural code -1-

Structural code -2- Here we use positional association. COMPONENT keyword is omitted (in general, it is optional).

Naming signals

Generate statement