The electronic circuits domain (and preparations for exercise) The circuit representation in chapter 8 is more detailed than necessary if we care only about the circuit functionality. A simpler formulation describes any m-input, n-output gate or circuit using a predicate with m+n arguments, such that the predicate is true exactly when the inputs and outputs were consistent. For example, NOT-gates are described by the binary predicate NOT(i,o), for which NOT(0,1) and NOT(1,0) are known. AND gates can be described by a ternary predicateAND(i1,i2,oa) where AND(0,0,0), AND(0,1,0), AND(1,0,0) and AND(1,1,1) are known.

Verification of composite circuits Composition of gates are defined by conjunctions of gate predicates in which shared variables indicate direct connections. For example, a NAND circuit can be composed from AND's and NOT's: i1,i2,oa,o AND(i1,i2,oa)  NOT(oa,o) NAND(i1,i2,o) To verify a NAND gate, we can simply verify that the following facts follows from the definitions: NAND(0,0,1) .NAND(0,1,1) .NAND(1,0,1) ,.NAND(1,1,0).

Verification of one bit full adder Figure 8.4 contains 3 types of gates: XOR –gates (X1,X2) AND-gates (A1,A2) OR-gates(O1) An instructive exercise will be to define this circuit in FOL, and specify how the circuit can be verified.